/** * @file dma.c * @author chipsea * @brief * @version 0.1 * @date 2020-11-30 * @copyright Copyright (c) 2020, CHIPSEA Co., Ltd. * @note */ #ifndef __DMA_H_ #define __DMA_H_ /* Includes ------------------------------------------------------------------- */ #ifdef __cplusplus extern "C" { #endif /* Public Macros -------------------------------------------------------------- */ /** @defgroup GPDMA_Public_Macros GPDMA Public Macros * @{ */ /** DMAC Connection number definitions */ typedef enum{ DMA_CONN_MEM=0,// ((0)) /*memory*/ DMA_CONN_SPI0_Tx=1,// ((0UL)) /** SSP0 Tx */ DMA_CONN_SPI0_Rx,// ((1UL)) /** SSP0 Rx */ DMA_CONN_SPI1_Tx,// ((2UL)) /** SSP1 Tx */ DMA_CONN_SPI1_Rx,// ((3UL)) /** SSP1 Rx */ DMA_CONN_I2C0_Tx=9,// ((8UL)) /** IIC0 Tx */ DMA_CONN_I2C0_Rx,// ((9UL)) /** IIC0 Rx */ DMA_CONN_I2C1_Tx,// ((10UL)) /** IIC1 Tx */ DMA_CONN_I2C1_Rx,// ((11UL)) /** IIC1 Rx */ DMA_CONN_UART0_Tx,// ((10UL)) /** UART0 Tx */ DMA_CONN_UART0_Rx,// ((11UL)) /** UART0 Rx */ DMA_CONN_UART1_Tx,// ((12UL)) /** UART1 Tx */ DMA_CONN_UART1_Rx,// ((13UL)) /** UART1 Rx */ } DMA_CONN_e; /** Burst size in Source and Destination definitions */ #define DMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */ #define DMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */ #define DMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */ #define DMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */ #define DMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */ #define DMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */ #define DMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */ #define DMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */ /** Width in Source transfer width and Destination transfer width definitions */ #define DMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */ #define DMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */ #define DMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */ #define DMA_WIDTH_2WORD ((3UL)) /**< Width = 8 bytes */ #define DMA_WIDTH_4WORD ((4UL)) /**< Width = 16 bytes */ #define DMA_WIDTH_8WORD ((5UL)) /**< Width = 32 bytes */ /** DMAC Address Increment definitions */ #define DMA_INC_INC ((0UL)) /**< Increment */ #define DMA_INC_DEC ((1UL)) /**< Decrement */ #define DMA_INC_NCHG ((2UL)) /**< No change */ /** * @} */ /* Private Macros ------------------------------------------------------------- */ /** @defgroup GPDMA_Private_Macros GPDMA Private Macros * @{ */ /* --------------------- BIT DEFINITIONS -------------------------------------- */ /*********************************************************************//** * Macro defines for DMA Interrupt Status register **********************************************************************/ #define DMA_DMACIntStat_Ch(n) (((1UL<