dma.h 13 KB

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  1. /**
  2. * @file dma.c
  3. * @author chipsea
  4. * @brief
  5. * @version 0.1
  6. * @date 2020-11-30
  7. * @copyright Copyright (c) 2020, CHIPSEA Co., Ltd.
  8. * @note
  9. */
  10. #ifndef __DMA_H_
  11. #define __DMA_H_
  12. /* Includes ------------------------------------------------------------------- */
  13. #ifdef __cplusplus
  14. extern "C"
  15. {
  16. #endif
  17. /* Public Macros -------------------------------------------------------------- */
  18. /** @defgroup GPDMA_Public_Macros GPDMA Public Macros
  19. * @{
  20. */
  21. /** DMAC Connection number definitions */
  22. typedef enum{
  23. DMA_CONN_MEM=0,// ((0)) /*memory*/
  24. DMA_CONN_SPI0_Tx=1,// ((0UL)) /** SSP0 Tx */
  25. DMA_CONN_SPI0_Rx,// ((1UL)) /** SSP0 Rx */
  26. DMA_CONN_SPI1_Tx,// ((2UL)) /** SSP1 Tx */
  27. DMA_CONN_SPI1_Rx,// ((3UL)) /** SSP1 Rx */
  28. DMA_CONN_I2C0_Tx=9,// ((8UL)) /** IIC0 Tx */
  29. DMA_CONN_I2C0_Rx,// ((9UL)) /** IIC0 Rx */
  30. DMA_CONN_I2C1_Tx,// ((10UL)) /** IIC1 Tx */
  31. DMA_CONN_I2C1_Rx,// ((11UL)) /** IIC1 Rx */
  32. DMA_CONN_UART0_Tx,// ((10UL)) /** UART0 Tx */
  33. DMA_CONN_UART0_Rx,// ((11UL)) /** UART0 Rx */
  34. DMA_CONN_UART1_Tx,// ((12UL)) /** UART1 Tx */
  35. DMA_CONN_UART1_Rx,// ((13UL)) /** UART1 Rx */
  36. } DMA_CONN_e;
  37. /** Burst size in Source and Destination definitions */
  38. #define DMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */
  39. #define DMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */
  40. #define DMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */
  41. #define DMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */
  42. #define DMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */
  43. #define DMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */
  44. #define DMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */
  45. #define DMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */
  46. /** Width in Source transfer width and Destination transfer width definitions */
  47. #define DMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */
  48. #define DMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */
  49. #define DMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */
  50. #define DMA_WIDTH_2WORD ((3UL)) /**< Width = 8 bytes */
  51. #define DMA_WIDTH_4WORD ((4UL)) /**< Width = 16 bytes */
  52. #define DMA_WIDTH_8WORD ((5UL)) /**< Width = 32 bytes */
  53. /** DMAC Address Increment definitions */
  54. #define DMA_INC_INC ((0UL)) /**< Increment */
  55. #define DMA_INC_DEC ((1UL)) /**< Decrement */
  56. #define DMA_INC_NCHG ((2UL)) /**< No change */
  57. /**
  58. * @}
  59. */
  60. /* Private Macros ------------------------------------------------------------- */
  61. /** @defgroup GPDMA_Private_Macros GPDMA Private Macros
  62. * @{
  63. */
  64. /* --------------------- BIT DEFINITIONS -------------------------------------- */
  65. /*********************************************************************//**
  66. * Macro defines for DMA Interrupt Status register
  67. **********************************************************************/
  68. #define DMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF))
  69. #define DMA_DMACIntStat_BITMASK ((0xFF))
  70. /*********************************************************************//**
  71. * Macro defines for DMA Interrupt Terminal Count Request Status register
  72. **********************************************************************/
  73. #define DMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF))
  74. #define DMA_DMACIntTCStat_BITMASK ((0xFF))
  75. /*********************************************************************//**
  76. * Macro defines for DMA Interrupt Terminal Count Request Clear register
  77. **********************************************************************/
  78. #define DMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF))
  79. #define DMA_DMACIntTCClear_BITMASK ((0xFF))
  80. /*********************************************************************//**
  81. * Macro defines for DMA Interrupt Error Status register
  82. **********************************************************************/
  83. #define DMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF))
  84. #define DMA_DMACIntErrStat_BITMASK ((0xFF))
  85. /*********************************************************************//**
  86. * Macro defines for DMA Interrupt Tfr Clear register
  87. **********************************************************************/
  88. #define DMA_DMACIntTfrClr_Ch(n) (((1UL<<n)&0xFF))
  89. #define DMA_DMACIntTfrClr_BITMASK ((0xFF))
  90. /*********************************************************************//**
  91. * Macro defines for DMA Interrupt Block Clear register
  92. **********************************************************************/
  93. #define DMA_DMACIntBlockClr_Ch(n) (((1UL<<n)&0xFF))
  94. #define DMA_DMACIntBlockClr_BITMASK ((0xFF))
  95. /*********************************************************************//**
  96. * Macro defines for DMA Interrupt SrcTran Clear register
  97. **********************************************************************/
  98. #define DMA_DMACIntSrcTranClr_Ch(n) (((1UL<<n)&0xFF))
  99. #define DMA_DMACIntSrcTranClr_BITMASK ((0xFF))
  100. /*********************************************************************//**
  101. * Macro defines for DMA Interrupt DstTran Clear register
  102. **********************************************************************/
  103. #define DMA_DMACIntDstTranClr_Ch(n) (((1UL<<n)&0xFF))
  104. #define DMA_DMACIntDstTranClr_BITMASK ((0xFF))
  105. /*********************************************************************//**
  106. * Macro defines for DMA Interrupt Error Clear register
  107. **********************************************************************/
  108. #define DMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF))
  109. #define DMA_DMACIntErrClr_BITMASK ((0xFF))
  110. /*********************************************************************//**
  111. * Macro defines for DMA Raw Interrupt Terminal Count Status register
  112. **********************************************************************/
  113. #define DMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF))
  114. #define DMA_DMACRawIntTCStat_BITMASK ((0xFF))
  115. /*********************************************************************//**
  116. * Macro defines for DMA Raw Error Interrupt Status register
  117. **********************************************************************/
  118. #define DMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF))
  119. #define DMA_DMACRawIntErrStat_BITMASK ((0xFF))
  120. /*********************************************************************//**
  121. * Macro defines for DMA Enabled Channel register
  122. **********************************************************************/
  123. #define DMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF))
  124. #define DMA_DMACEnbldChns_BITMASK ((0xFF))
  125. /*********************************************************************//**
  126. * Macro defines for DMA Software Burst Request register
  127. **********************************************************************/
  128. #define DMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF))
  129. #define DMA_DMACSoftBReq_BITMASK ((0xFFFF))
  130. /*********************************************************************//**
  131. * Macro defines for DMA Software Single Request register
  132. **********************************************************************/
  133. #define DMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF))
  134. #define DMA_DMACSoftSReq_BITMASK ((0xFFFF))
  135. /*********************************************************************//**
  136. * Macro defines for DMA Software Last Burst Request register
  137. **********************************************************************/
  138. #define DMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF))
  139. #define DMA_DMACSoftLBReq_BITMASK ((0xFFFF))
  140. /*********************************************************************//**
  141. * Macro defines for DMA Software Last Single Request register
  142. **********************************************************************/
  143. #define DMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF))
  144. #define DMA_DMACSoftLSReq_BITMASK ((0xFFFF))
  145. /*********************************************************************//**
  146. * Macro defines for DMA Configuration register
  147. **********************************************************************/
  148. #define DMA_DMAC_E ((0x01)) /**< DMA Controller enable*/
  149. #define DMA_DMAC_D ((0x00)) /**< DMA Controller disable*/
  150. #define DMA_DMAC_INT_E ((0x01)) /**< DMA Controller Interrupt enable*/
  151. /*********************************************************************//**
  152. * Macro defines for DMA Synchronization register
  153. **********************************************************************/
  154. #define DMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF))
  155. #define DMA_DMACSync_BITMASK ((0xFFFF))
  156. /*********************************************************************//**
  157. * Macro defines for DMA Request Select register
  158. **********************************************************************/
  159. #define DMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF))
  160. #define DMA_DMAReqSel_BITMASK ((0xFF))
  161. /*********************************************************************//**
  162. * Macro defines for DMA Channel Linked List Item registers
  163. **********************************************************************/
  164. /** DMAC Channel Linked List Item registers bit mask*/
  165. #define DMA_DMACCxLLI_BITMASK ((0xFFFFFFFC))
  166. /*********************************************************************//**
  167. * Macro defines for DMA channel control registers
  168. **********************************************************************/
  169. /** Transfer size*/
  170. #define DMA_DMACCxControl_TransferSize(n) (n&0x7FF)
  171. /** Source burst size*/
  172. #define DMA_DMACCxControl_SMSize(n) (((n&0x07)<<14))
  173. /** Destination burst size*/
  174. #define DMA_DMACCxControl_DMSize(n) (((n&0x07)<<11))
  175. /** Source transfer width*/
  176. #define DMA_DMACCxControl_SWidth(n) (((n&0x07)<<4))
  177. /** Destination transfer width*/
  178. #define DMA_DMACCxControl_DWidth(n) (((n&0x07)<<1))
  179. /** Source increment*/
  180. #define DMA_DMACCxControl_SInc(n) (((n&0x03)<<9))
  181. /** Destination increment*/
  182. #define DMA_DMACCxControl_DInc(n) (((n&0x03)<<7))
  183. /*********************************************************************//**
  184. * Macro defines for DMA Channel Configuration registers
  185. **********************************************************************/
  186. /** DMAC channel write bit enable*/
  187. #define DMA_DMACCxConfig_E(n) ((0x100UL<<n))
  188. /** DMAC channel int mask bit enable*/
  189. #define DMA_DMACCxIntMask_E(n) ((0x100UL<<n))
  190. /** Source peripheral*/
  191. #define DMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)))
  192. /** Destination peripheral*/
  193. #define DMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<4))
  194. /** This value indicates the type of transfer*/
  195. #define DMA_DMACCxConfig_TransferType(n) (((n&0x7)<<20))
  196. /** Interrupt error mask*/
  197. #define DMA_DMACCxConfig_IE ((1UL<<14))
  198. /** Terminal count interrupt mask*/
  199. #define DMA_DMACCxConfig_ITC ((1UL<<15))
  200. /** Lock*/
  201. #define DMA_DMACCxConfig_L ((1UL<<16))
  202. /** Active*/
  203. #define DMA_DMACCxConfig_A ((1UL<<17))
  204. /** Halt*/
  205. #define DMA_DMACCxConfig_H ((1UL<<18))
  206. /** DMAC Channel Configuration registers bit mask */
  207. #define DMA_DMACCxConfig_BITMASK ((0x7FFFF))
  208. /**
  209. * @}
  210. */
  211. #define DMA_TRANSFERTYPE_M2M ((0UL))
  212. /** DMAC Transfer type definitions: Memory to peripheral - DMA control */
  213. #define DMA_TRANSFERTYPE_M2P ((1UL))
  214. /** DMAC Transfer type definitions: Peripheral to memory - DMA control */
  215. #define DMA_TRANSFERTYPE_P2M ((2UL))
  216. /** DMAC Source peripheral to destination peripheral - DMA control */
  217. #define DMA_TRANSFERTYPE_P2P ((3UL))
  218. /** If dstnation address is flash, should set this bit- DMA control */
  219. #define DMA_DST_XIMT_IS_FLASH ((0UL))
  220. /** DMAC Source peripheral to destination peripheral - DMA control */
  221. #define DMA_DST_XIMT_NOT_FLASH ((1UL))
  222. #define DMA_GET_MAX_TRANSPORT_SIZE(ch) ((ch == DMA_CH_0) ? 0x7ff : 0x1f)
  223. /**
  224. * @brief DMAC Interrupt clear status enumeration
  225. */
  226. typedef enum{
  227. DMA_STATCLR_INTTC, /**< GPDMA Interrupt Terminal Count Request Clear */
  228. DMA_STATCLR_INTERR /**< GPDMA Interrupt Error Clear */
  229. }DMA_StateClear_Type;
  230. /**
  231. * @brief DMAC Channel configuration structure type definition
  232. */
  233. typedef struct {
  234. uint32_t transf_size; /**< Length/Size of transfer */
  235. uint8_t sinc;
  236. uint8_t src_tr_width;
  237. uint8_t src_msize;
  238. uint32_t src_addr;
  239. uint8_t dinc;
  240. uint8_t dst_tr_width;
  241. uint8_t dst_msize;
  242. uint32_t dst_addr;
  243. bool enable_int;
  244. } DMA_CH_CFG_t;
  245. typedef enum{
  246. DMA_CH_0 = 0,
  247. DMA_CH_1,
  248. DMA_CH_2,
  249. DMA_CH_3,
  250. DMA_CH_NUM,
  251. } DMA_CH_t;
  252. /**
  253. * @brief DMAC Linker List Item structure type definition
  254. */
  255. typedef struct {
  256. uint32_t src_addr; /**< Source Address */
  257. uint32_t dst_addr; /**< Destination address */
  258. uint32_t lli; /**< Next LLI address, otherwise set to '0' */
  259. uint32_t ctrl; /**< GPDMA Control of this LLI */
  260. } DMA_LLI_t;
  261. /**
  262. * @brief DMAC callback definition
  263. */
  264. typedef void (*DMA_Hdl_t)(DMA_CH_t);
  265. typedef struct {
  266. DMA_CH_t dma_channel;
  267. DMA_Hdl_t evt_handler;
  268. }HAL_DMA_t;
  269. typedef struct {
  270. uint8_t init_ch;
  271. uint8_t interrupt;
  272. uint8_t xmit_busy;
  273. uint8_t xmit_flash;
  274. DMA_Hdl_t evt_handler;
  275. } DMA_CH_Ctx_t;
  276. int HalDMAInitChannel(HAL_DMA_t cfg);
  277. int HalDMAConfigChannel(DMA_CH_t ch, DMA_CH_CFG_t* cfg);
  278. int HalDMAStartChannel(DMA_CH_t ch);
  279. int HalDMAStopChannel(DMA_CH_t ch);
  280. int HalDMAWaitChannelComplete(DMA_CH_t ch);
  281. int HalDMAStatusControl(DMA_CH_t ch);
  282. int HalDMAInit(void);
  283. int HalDMADeinit(void);
  284. void __attribute__((used)) HalDMAIRQHandler(void);
  285. #ifdef __cplusplus
  286. }
  287. #endif
  288. #endif
  289. /**
  290. * @}
  291. */
  292. /* --------------------------------- End Of File ------------------------------ */