uart.c 15 KB

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  1. /**
  2. * @file uart.c
  3. * @author chipsea
  4. * @brief
  5. * @version 0.1
  6. * @date 2020-11-30
  7. * @copyright Copyright (c) 2020, CHIPSEA Co., Ltd.
  8. * @note
  9. */
  10. #include "sdk_config.h"
  11. #include "rom_sym_def.h"
  12. #include <string.h>
  13. #include "cst92f2x.h"
  14. #include "mcu.h"
  15. #include "gpio.h"
  16. #include "clock.h"
  17. #include "uart.h"
  18. #include "pwrmgr.h"
  19. #include "error.h"
  20. #include "jump_function.h"
  21. #define UART_TX_BUFFER_SIZE 256
  22. typedef struct _uart_Context{
  23. bool enable;
  24. uint8_t tx_state;
  25. uart_Tx_Buf_t tx_buf;
  26. uart_Cfg_t cfg;
  27. }uart_Ctx_t;
  28. static uart_Ctx_t m_uartCtx[2] = {
  29. {.enable = FALSE,},
  30. {.enable = FALSE,},
  31. };
  32. static ErrCode_t txmit_buf_use_tx_buf(UART_INDEX_e uart_index,uint8_t *buf,uint16_t len)
  33. {
  34. uart_Tx_Buf_t* p_txbuf = &(m_uartCtx[uart_index].tx_buf);
  35. uint8_t* p_data;
  36. AP_UART_TypeDef * cur_uart = (AP_UART_TypeDef *) AP_UART0_BASE;
  37. if(len == 0 || buf == NULL)
  38. return ERR_INVALID_PARAM;
  39. if(p_txbuf->tx_state == TX_STATE_UNINIT)
  40. return ERR_NO_MEM;
  41. if(p_txbuf->tx_buf_size < len)
  42. return ERR_NO_MEM;
  43. if(p_txbuf->tx_state != TX_STATE_IDLE)
  44. {
  45. if(p_txbuf->tx_data_size + len > p_txbuf->tx_buf_size)
  46. return ERR_NO_MEM;
  47. HAL_ENTER_CRITICAL_SECTION();
  48. memcpy(p_txbuf->tx_buf + p_txbuf->tx_data_size, buf, len);
  49. p_txbuf->tx_data_size += len;
  50. HAL_EXIT_CRITICAL_SECTION();
  51. return ERR_NONE;
  52. }
  53. memcpy(p_txbuf->tx_buf, buf, len);
  54. p_txbuf->tx_data_size = len;
  55. p_txbuf->tx_data_offset = 0;
  56. p_txbuf->tx_state = TX_STATE_TX;
  57. p_data = p_txbuf->tx_buf;
  58. // len = p_txbuf->tx_data_size - p_txbuf->tx_data_offset;
  59. len = len > UART_TX_FIFO_SIZE ? UART_TX_FIFO_SIZE : len;
  60. if(uart_index == UART1)
  61. cur_uart = (AP_UART_TypeDef *) AP_UART1_BASE;
  62. cur_uart->IER &= ~(IER_ETBEI);
  63. while(len--){
  64. cur_uart->THR = p_data[p_txbuf->tx_data_offset++];
  65. }
  66. if(uart_index == UART0)
  67. hal_pwrmgr_lock(MOD_UART0);
  68. else
  69. hal_pwrmgr_lock(MOD_UART1);
  70. cur_uart->IER |= IER_ETBEI;
  71. return ERR_NONE;
  72. }
  73. static ErrCode_t txmit_buf_polling(UART_INDEX_e uart_index,uint8_t *buf,uint16_t len)
  74. {
  75. //volatile int timeout = 0;
  76. AP_UART_TypeDef * cur_uart = (AP_UART_TypeDef *) AP_UART0_BASE;
  77. if(uart_index == UART1)
  78. cur_uart = (AP_UART_TypeDef *) AP_UART1_BASE;
  79. HAL_WAIT_CONDITION_TIMEOUT(!(cur_uart->USR & USR_BUSY), 100000);
  80. while(len--)
  81. {
  82. HAL_WAIT_CONDITION_TIMEOUT((cur_uart->LSR & LSR_THRE), 100000);
  83. cur_uart->THR = *buf++;
  84. //timeout=0;
  85. }
  86. //wait shift register empty
  87. HAL_WAIT_CONDITION_TIMEOUT((cur_uart->LSR & LSR_TEMT), 100000);
  88. return ERR_NONE;
  89. }
  90. static void __ATTR_SECTION_SRAM__ irq_rx_handler(UART_INDEX_e uart_index,uint8_t flg)
  91. {
  92. int i;
  93. uint8_t data[UART_RX_FIFO_SIZE];
  94. uint8_t len;
  95. AP_UART_TypeDef *cur_uart = (AP_UART_TypeDef *)AP_UART0_BASE;
  96. if(uart_index == UART1){
  97. cur_uart = (AP_UART_TypeDef *) AP_UART1_BASE;
  98. }
  99. if(m_uartCtx[uart_index].cfg.use_fifo){
  100. len = cur_uart->RFL;
  101. for(i = 0; i< len; i++)
  102. data[i] = (uint8_t)(cur_uart->RBR & 0xff);
  103. }
  104. else{
  105. len = 1;
  106. cur_uart->LSR; //clear interrupt
  107. data[0] = (uint8_t)(cur_uart->RBR & 0xff);
  108. }
  109. if(m_uartCtx[uart_index].cfg.evt_handler){
  110. uart_Evt_t evt;
  111. evt.type = flg;
  112. evt.data = data;
  113. evt.len = len;
  114. m_uartCtx[uart_index].cfg.evt_handler(&evt);
  115. }
  116. }
  117. static void __ATTR_SECTION_SRAM__ irq_tx_empty_handler(UART_INDEX_e uart_index)
  118. {
  119. uart_Tx_Buf_t* p_txbuf = &(m_uartCtx[uart_index].tx_buf);
  120. uint8_t* p_data;
  121. uint16_t len;
  122. AP_UART_TypeDef *cur_uart = (AP_UART_TypeDef *)AP_UART0_BASE;
  123. if(m_uartCtx[uart_index].enable == FALSE)
  124. return;
  125. if(m_uartCtx[uart_index].cfg.use_fifo == FALSE)
  126. return;
  127. if(m_uartCtx[uart_index].cfg.use_tx_buf == FALSE)
  128. return;
  129. if(p_txbuf->tx_state != TX_STATE_TX)
  130. return;
  131. p_data = p_txbuf->tx_buf;
  132. len = p_txbuf->tx_data_size - p_txbuf->tx_data_offset;
  133. len = len > UART_TX_FIFO_SIZE ? UART_TX_FIFO_SIZE : len;
  134. if(len == 0){
  135. p_txbuf->tx_state = TX_STATE_IDLE;
  136. p_txbuf->tx_data_offset = 0;
  137. p_txbuf->tx_data_size = 0;
  138. if(m_uartCtx[uart_index].cfg.evt_handler){
  139. uart_Evt_t evt = {
  140. .type = UART_EVT_TYPE_TX_COMPLETED,
  141. .data = NULL,
  142. .len = 0,
  143. };
  144. m_uartCtx[uart_index].cfg.evt_handler(&evt);
  145. }
  146. if(UART0 == uart_index)
  147. hal_pwrmgr_unlock(MOD_UART0);
  148. else
  149. hal_pwrmgr_unlock(MOD_UART1);
  150. return;
  151. }
  152. if(uart_index == UART1)
  153. cur_uart = (AP_UART_TypeDef *) AP_UART1_BASE;
  154. while(len--){
  155. cur_uart->THR = p_data[p_txbuf->tx_data_offset++];
  156. }
  157. }
  158. static int uart_hw_deinit(UART_INDEX_e uart_index)
  159. {
  160. MODULE_e mod = MOD_UART0;
  161. IRQn_Type irq_type = UART0_IRQn;
  162. AP_UART_TypeDef * cur_uart = AP_UART0;
  163. if(uart_index== UART1){
  164. mod = MOD_UART1;
  165. irq_type = UART1_IRQn;
  166. cur_uart = AP_UART1;
  167. }
  168. NVIC_DisableIRQ(irq_type);
  169. HalGpioFmuxEnable(m_uartCtx[uart_index].cfg.tx_pin,Bit_DISABLE);
  170. HalGpioFmuxEnable(m_uartCtx[uart_index].cfg.rx_pin,Bit_DISABLE);
  171. cur_uart->LCR=0x80;
  172. cur_uart->DLM=0;
  173. cur_uart->DLL=0;
  174. cur_uart->LCR =0;
  175. cur_uart->FCR=0;
  176. cur_uart->IER = 0;
  177. //hal_clk_gate_enable(mod);
  178. hal_clk_reset(mod);
  179. hal_clk_gate_disable(mod);
  180. if(uart_index== UART0){
  181. JUMP_FUNCTION(UART0_IRQ_HANDLER) = 0;
  182. }
  183. else{
  184. JUMP_FUNCTION(UART1_IRQ_HANDLER) = 0;
  185. }
  186. return ERR_NONE;
  187. }
  188. static int uart_hw_init(UART_INDEX_e uart_index)
  189. {
  190. uart_Cfg_t* pcfg;
  191. int pclk = clk_get_pclk();
  192. uint32_t dll;
  193. AP_UART_TypeDef * cur_uart = AP_UART0;
  194. MODULE_e mod = MOD_UART0;
  195. IRQn_Type irq_type = UART0_IRQn;
  196. gpio_fmux_e fmux_tx = FMUX_UART0_TX, fmux_rx = FMUX_UART0_RX;
  197. uart_hw_deinit(uart_index);
  198. if(uart_index== UART1){
  199. cur_uart = AP_UART1;
  200. mod = MOD_UART1;
  201. irq_type = UART1_IRQn;
  202. fmux_tx = FMUX_UART1_TX;
  203. fmux_rx = FMUX_UART1_RX;
  204. }
  205. if((m_uartCtx[uart_index].cfg.tx_pin == GPIO_DUMMY) && (m_uartCtx[uart_index].cfg.rx_pin == GPIO_DUMMY))
  206. return ERR_INVALID_PARAM;
  207. pcfg = &(m_uartCtx[uart_index].cfg);
  208. hal_clk_gate_enable(mod);
  209. hal_clk_reset(mod);
  210. // if(m_uartCtx[uart_index].enable == FALSE){
  211. // HalGpioFmuxEnable(P9, Bit_DISABLE);
  212. // HalGpioFmuxEnable(P10, Bit_DISABLE);
  213. // }
  214. HalGpioPupdConfig(pcfg->tx_pin, GPIO_PULL_UP);
  215. HalGpioPupdConfig(pcfg->rx_pin, GPIO_PULL_UP);
  216. HalGpioFmuxConfig(pcfg->tx_pin, fmux_tx);
  217. HalGpioFmuxConfig(pcfg->rx_pin, fmux_rx);
  218. cur_uart->LCR =0;
  219. dll = ((pclk>>4)+(pcfg->baudrate>>1))/pcfg->baudrate;
  220. cur_uart->MCR=0x0;
  221. cur_uart->LCR=0x80;
  222. cur_uart->DLM=(dll & 0xFF00) >> 8;
  223. cur_uart->DLL=(dll & 0xFF);
  224. if(pcfg->parity)
  225. cur_uart->LCR = 0x1b; //8bit, 1 stop even parity
  226. else
  227. cur_uart->LCR = 0x3; //8bit, 1 stop no parity
  228. if(pcfg->use_fifo)//set fifo, enable tx FIFO mode(empty trigger), rx FIFO mode(1/2 trigger)
  229. cur_uart->FCR= FCR_TX_FIFO_RESET|FCR_RX_FIFO_RESET|FCR_FIFO_ENABLE|UART_FIFO_RX_TRIGGER|UART_FIFO_TX_TRIGGER;
  230. else
  231. cur_uart->FCR=0;
  232. //enable Received Data Available Interrupt
  233. cur_uart->IER = IER_ERBFI;
  234. if(pcfg->use_fifo)
  235. cur_uart->IER |= IER_PTIME;
  236. if(pcfg->use_tx_buf)
  237. cur_uart->IER |= IER_ETBEI;
  238. if(uart_index== UART0){
  239. JUMP_FUNCTION(UART0_IRQ_HANDLER) = (uint32_t)&HalUart0IRQHandler;
  240. }
  241. else{
  242. JUMP_FUNCTION(UART1_IRQ_HANDLER) = (uint32_t)&HalUart1IRQHandler;
  243. }
  244. NVIC_SetPriority(irq_type, IRQ_PRIO_HAL);
  245. NVIC_EnableIRQ(irq_type);
  246. return ERR_NONE;
  247. }
  248. /**************************************************************************************
  249. * @fn HalUart0IRQHandler
  250. *
  251. * @brief This function process for uart interrupt
  252. *
  253. * input parameters
  254. *
  255. * @param None.
  256. *
  257. * output parameters
  258. *
  259. * @param None.
  260. *
  261. * @return None.
  262. **************************************************************************************/
  263. void __ATTR_SECTION_SRAM__ HalUart0IRQHandler(void)
  264. {
  265. uint8_t IRQ_ID= (AP_UART0->IIR & 0x0f);
  266. //if(m_uartCtx[UART0].enable == FALSE)
  267. // return;
  268. switch(IRQ_ID)
  269. {
  270. case TIMEOUT_IRQ:
  271. irq_rx_handler(UART0,UART_EVT_TYPE_RX_DATA_TO);
  272. break;
  273. case RDA_IRQ:
  274. irq_rx_handler(UART0,UART_EVT_TYPE_RX_DATA);
  275. break;
  276. case THR_EMPTY:
  277. irq_tx_empty_handler(UART0);
  278. break;
  279. case RLS_IRQ:
  280. break;
  281. case BUSY_IRQ:
  282. (void)AP_UART0->USR;
  283. break;
  284. default:
  285. break;
  286. }
  287. }
  288. void __ATTR_SECTION_SRAM__ HalUart1IRQHandler(void)
  289. {
  290. uint8_t IRQ_ID= (AP_UART1->IIR & 0x0f);
  291. //if(m_uartCtx[UART1].enable == FALSE)
  292. // return;
  293. switch(IRQ_ID)
  294. {
  295. case TIMEOUT_IRQ:
  296. irq_rx_handler(UART1,UART_EVT_TYPE_RX_DATA_TO);
  297. break;
  298. case RDA_IRQ:
  299. irq_rx_handler(UART1,UART_EVT_TYPE_RX_DATA);
  300. break;
  301. case THR_EMPTY:
  302. irq_tx_empty_handler(UART1);
  303. break;
  304. case RLS_IRQ:
  305. break;
  306. case BUSY_IRQ:
  307. (void)AP_UART1->USR;
  308. break;
  309. default:
  310. break;
  311. }
  312. }
  313. /**
  314. * @fn ErrCode_t HalUartRegister(UART_INDEX_e uart_index, uart_Hdl_t cb)
  315. * @brief the uart register receive callback
  316. * @param cb - receive callback
  317. * @return error code.
  318. */
  319. ErrCode_t HalUartRegister(UART_INDEX_e uart_index, uart_Hdl_t cb)
  320. {
  321. if(uart_index > UART1 || m_uartCtx[uart_index].enable != TRUE)
  322. {
  323. return ERR_INVALID_PARAM;
  324. }
  325. m_uartCtx[uart_index].cfg.evt_handler = cb;
  326. return ERR_NONE;
  327. }
  328. /**
  329. * @fn ErrCode_t HalUartUnRegister(UART_INDEX_e uart_index)
  330. * @brief the uart unregister receive callback
  331. * @param None
  332. * @return error code.
  333. */
  334. ErrCode_t HalUartUnRegister(UART_INDEX_e uart_index)
  335. {
  336. if (m_uartCtx[uart_index].enable != TRUE || uart_index > UART1)
  337. {
  338. return ERR_INVALID_PARAM;
  339. }
  340. m_uartCtx[uart_index].cfg.evt_handler = NULL;
  341. return ERR_NONE;
  342. }
  343. static void uart_wakeup_process_0(void)
  344. {
  345. uart_hw_init(UART0);
  346. }
  347. static void uart_wakeup_process_1(void)
  348. {
  349. uart_hw_init(UART1);
  350. }
  351. /**
  352. * @fn ErrCode_t HalUartInit(UART_INDEX_e uart_index, uart_Cfg_t cfg)
  353. * @brief the uart Initialization
  354. * @param cfg - peripheral configuration
  355. * @return error code.
  356. */
  357. ErrCode_t HalUartInit(UART_INDEX_e uart_index, uart_Cfg_t cfg)
  358. {
  359. if(uart_index != UART0 && uart_index != UART1)
  360. {
  361. return ERR_NOT_SUPPORTED;
  362. }
  363. if(m_uartCtx[uart_index].enable)
  364. {
  365. return ERR_BUSY;
  366. }
  367. if(cfg.hw_fwctrl)
  368. {
  369. return ERR_NOT_SUPPORTED;
  370. }
  371. if(cfg.tx_pin >= GPIO_NUM || cfg.rx_pin >= GPIO_NUM || cfg.tx_pin == cfg.rx_pin)
  372. {
  373. return ERR_INVALID_PARAM;
  374. }
  375. memset(&(m_uartCtx[uart_index]), 0, sizeof(uart_Ctx_t));
  376. memcpy(&(m_uartCtx[uart_index].cfg), &cfg, sizeof(uart_Cfg_t));
  377. uart_hw_init(uart_index);
  378. m_uartCtx[uart_index].enable = TRUE;
  379. if(uart_index == UART0)
  380. hal_pwrmgr_register(MOD_UART0, NULL, uart_wakeup_process_0);
  381. else
  382. hal_pwrmgr_register(MOD_UART1, NULL, uart_wakeup_process_1);
  383. return ERR_NONE;
  384. }
  385. ErrCode_t HalUartDeInit(UART_INDEX_e uart_index)
  386. {
  387. if(uart_index != UART0 && uart_index != UART1)
  388. {
  389. return ERR_NOT_SUPPORTED;
  390. }
  391. if(!m_uartCtx[uart_index].enable)
  392. {
  393. return ERR_INVALID_STATE;
  394. }
  395. uart_hw_deinit(uart_index);
  396. memset(&(m_uartCtx[uart_index]), 0, sizeof(m_uartCtx));
  397. m_uartCtx[uart_index].enable = FALSE;
  398. if(uart_index == UART0)
  399. hal_pwrmgr_unregister(MOD_UART0);
  400. else
  401. hal_pwrmgr_unregister(MOD_UART1);
  402. return ERR_NONE;
  403. }
  404. ErrCode_t HalUartSetTxBuf(UART_INDEX_e uart_index,uint8_t* buf, uint16_t size)
  405. {
  406. if(uart_index != UART0 && uart_index != UART1)
  407. {
  408. return ERR_NOT_SUPPORTED;
  409. }
  410. uart_Tx_Buf_t* p_txbuf = &(m_uartCtx[uart_index].tx_buf);
  411. if(buf == NULL || size ==0)
  412. {
  413. return ERR_INVALID_DATA;
  414. }
  415. if(m_uartCtx[uart_index].enable == FALSE)
  416. return ERR_INVALID_STATE;
  417. if(m_uartCtx[uart_index].cfg.use_tx_buf == FALSE)
  418. return ERR_NOT_SUPPORTED;
  419. if(p_txbuf->tx_state != TX_STATE_UNINIT)
  420. return ERR_INVALID_STATE;
  421. HAL_ENTER_CRITICAL_SECTION();
  422. p_txbuf->tx_buf = buf;
  423. p_txbuf->tx_buf_size = size;
  424. p_txbuf->tx_data_offset = 0;
  425. p_txbuf->tx_data_size= 0;
  426. p_txbuf->tx_state = TX_STATE_IDLE;
  427. HAL_EXIT_CRITICAL_SECTION();
  428. return ERR_NONE;
  429. }
  430. ErrCode_t HalUartGetTxReady(UART_INDEX_e uart_index)
  431. {
  432. if(uart_index > UART1)
  433. {
  434. return ERR_INVALID_PARAM;
  435. }
  436. if(m_uartCtx[uart_index].cfg.use_tx_buf == FALSE)
  437. return ERR_NONE;
  438. if(m_uartCtx[uart_index].tx_buf.tx_state == TX_STATE_IDLE)
  439. return ERR_NONE;
  440. return ERR_BUSY;
  441. }
  442. ErrCode_t HalUartSendBuf(UART_INDEX_e uart_index, uint8_t *buff, uint16_t len)
  443. {
  444. if(uart_index != UART0 && uart_index != UART1)
  445. {
  446. return ERR_NOT_SUPPORTED;
  447. }
  448. if(m_uartCtx[uart_index].cfg.use_tx_buf){
  449. return txmit_buf_use_tx_buf(uart_index,buff,len);
  450. }
  451. return txmit_buf_polling(uart_index,buff,len);
  452. }
  453. ErrCode_t HalUartSendByte(UART_INDEX_e uart_index, unsigned char data)
  454. {
  455. if(uart_index != UART0 && uart_index != UART1)
  456. {
  457. return ERR_NOT_SUPPORTED;
  458. }
  459. if(m_uartCtx[uart_index].enable != TRUE )
  460. {
  461. return ERR_INVALID_STATE;
  462. }
  463. AP_UART_TypeDef * cur_uart = (AP_UART_TypeDef *) AP_UART0_BASE;
  464. if(uart_index == UART1)
  465. cur_uart = (AP_UART_TypeDef *) AP_UART1_BASE;
  466. HAL_WAIT_CONDITION_TIMEOUT((cur_uart->LSR & LSR_THRE), 10000);
  467. cur_uart->THR=data;
  468. HAL_WAIT_CONDITION_TIMEOUT((cur_uart->LSR & LSR_TEMT), 10000);
  469. return ERR_NONE;
  470. }
  471. /**
  472. * @fn void HalUartBaudSet(UART_INDEX_e uart_index, uint32 baud)
  473. * @brief the uart baud set
  474. * @param[in] none
  475. * @return none.
  476. */
  477. void HalUartBaudSet(UART_INDEX_e uart_index, uint32 baud)
  478. {
  479. uint32_t dll;
  480. uint32_t pclk = clk_get_pclk();
  481. AP_UART_TypeDef * cur_uart = AP_UART0;
  482. if(uart_index == UART1)
  483. {
  484. cur_uart = AP_UART1;
  485. }
  486. m_uartCtx[uart_index].cfg.baudrate = baud;
  487. cur_uart->LCR = 0;
  488. dll = ((pclk>>4)+(baud>>1))/baud;
  489. cur_uart->MCR = 0x0;
  490. cur_uart->LCR = 0x80;
  491. cur_uart->DLM = (dll & 0xFF00) >> 8;
  492. cur_uart->DLL = (dll & 0xFF);
  493. if(m_uartCtx[uart_index].cfg.parity)
  494. cur_uart->LCR = 0x1b; //8bit, 1 stop even parity
  495. else
  496. cur_uart->LCR = 0x3; //8bit, 1 stop no parity
  497. }
  498. /**
  499. * @fn ErrCode_t HalUartGetBusy(UART_INDEX_e uart_index)
  500. * @brief the uart busy get
  501. * @param[in] none
  502. * @return none.
  503. */
  504. ErrCode_t HalUartGetBusy(UART_INDEX_e uart_index)
  505. {
  506. AP_UART_TypeDef * cur_uart = AP_UART0;
  507. if(uart_index != UART0 && uart_index != UART1)
  508. {
  509. return ERR_NOT_SUPPORTED;
  510. }
  511. if(!m_uartCtx[uart_index].enable)
  512. {
  513. return ERR_INVALID_STATE;
  514. }
  515. if(uart_index == UART1)
  516. {
  517. cur_uart = AP_UART1;
  518. }
  519. if( (!(cur_uart->LSR & LSR_TEMT)) || (cur_uart->USR & USR_BUSY) )
  520. {
  521. return ERR_BUSY;
  522. }
  523. return ERR_NONE;
  524. }