/**
 * Copyright 2016, yichip Semiconductor(shenzhen office)
 * All Rights Reserved.
 *
 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Yichip Semiconductor;
 * the contents of this file may not be disclosed to third parties, copied
 * or duplicated in any form, in whole or in part, without the prior
 * written permission of Yichip Semiconductor.
 */
  
/** 
  *@file drv_mic.h
  *@brief mic support for application.
  */
#ifndef _DRV_MIC_H_
#define _DRV_MIC_H_

#include "ipc.h"
#include <stdbool.h>
#include <stdio.h>

/**
  *@brief ADC configure.
  */
#define DRV_ADC_M0RAM_ENABLE	0x40
#define DRV_ADC_FILTER_DISABLE	0x20
#define DRV_ADC_ENABLE			0x80
#define DRV_ADC_8K_FILTer		0x10
#define DRV_ADC_16K_FILTer		0x00
#define DRV_ADC_CLEAR_RSSI		0x08
#define DRV_ADC_AVG_TIMER_RSSI  0x06
#define DRV_ADC_RSSI_CLOCK	 	0x01

/**
  *@brief ADC gpio.
  */
#define DRV_ADC_CHANNEL_SIG_GPIO6		0x0001
#define DRV_ADC_CHANNEL_SIG_GPIO7		0x0002
#define DRV_ADC_CHANNEL_SIG_GPIO8		0x0004
#define DRV_ADC_CHANNEL_SIG_GPIO9		0x0008
#define DRV_ADC_CHANNEL_SIG_GPIO10		0x0010
#define DRV_ADC_CHANNEL_SIG_GPIO11		0x0020
#define DRV_ADC_CHANNEL_SIG_GPIO12		0x0040
#define DRV_ADC_CHANNEL_SIG_GPIO13		0x0080
#define DRV_ADC_CHANNEL_DIFF_GPIO67		0x0100
#define DRV_ADC_CHANNEL_DIFF_GPIO89		0x0200
#define DRV_ADC_CHANNEL_DIFF_GPIO1011	0x0400
#define DRV_ADC_CHANNEL_DIFF_GPIO1213	0x0800


#define ENCODE_INPUT_LEN 		80
#define ENCODE_OUTPUT_LEN 		20
#define ENCODE_PACKET_NUM 		6

#define MIC_QUEUE_MAX 100
#define MIC_ADPCM_PACKET_LEN 24

#define ENCODE_PACKETS_LEN (ENCODE_INPUT_LEN*ENCODE_PACKET_NUM)

#define RECORE_BUFFER_SIZE 2400


typedef unsigned int uint;
typedef signed short s16;
/**
  *@brief ADC driver Configure definition.
  */
typedef struct
{
	unsigned char *mDmaBuf;	/*!< adc DMA start address */
	int16_t mDmaBufLen;		/*!< adc DMA buffer length */
	uint16_t mSampleDelay;	/*!< adc channel switch delay counter, based on 3M */
	uint16_t mChannelCfg;	/*!< adc channel switch */
	uint8_t mAdcConfig;		/*!< adc ctrl byte */
} DRV_ADC_CONFIG;


/**
  *@brief Microphone state enum.
  */
typedef enum
{
	MIC_DISABLE,
	MIC_ENABLE
}MIC_STATUS_ENUM;

/**
  *@brief Microphone current variable.
  */
typedef struct
{
	unsigned char *mReadBufPtr;	/*!< the pointer of microphone read buffer start */
	unsigned char *mReadPtr;	/*!< Microphone read pointer*/
	unsigned char *mEndPtr;		/*!< the pointer of microphone read buffer ending*/
	MIC_STATUS_ENUM mMicEnable;	/*!< microphone enable */
	MIC_STATUS_ENUM mMicBleEnable;/*!< microphone ble enable*/
}MIC_CUR_VARIABLE;


/**
  *@brief Queue header.
  */
typedef struct
{
	void *pHead;		/*!< Header pointer*/
	void *pWrite;		/*!< Writing queue pointer*/
	void *pRead;		/*!< Reading queue pointer*/
	uint8_t unit_Len;	/*!< size of element */
	uint8_t array_Len;	/*!< the length of array */
	uint8_t current_queue_len;/*!< Entire queue length */
}QUEUE_HEADER;

typedef void (*tMicCallback)(IPC_DATA_FORMAT *,int);

bool queue_init(QUEUE_HEADER *pQheader, void *pMem, uint8_t unitLen, uint8_t len);
bool queue_clear(QUEUE_HEADER *pQheader);
void * Delete_Queue(QUEUE_HEADER *pQheader);
bool queue_is_empty(QUEUE_HEADER *pQheader);
bool queue_is_full(QUEUE_HEADER *pQheader);
bool Insert_Queue(QUEUE_HEADER *pQheader,void *pEle);
void Drv_micQueueInit();
bool Drv_micQueueEmpty(QUEUE_HEADER *pQheader);
void Drv_micClearQueue();
void Drv_adcdma_init(DRV_ADC_CONFIG *pAdcConfig);
void Drv_adc_enable(void);
unsigned short Drv_adc_getWptr(void);
void Drv_adc_disable(void);
void DRV_Mic_Init(void);
void DRV_Mic_DeInit(void);
void DRV_Mic_sendEnable();
void DRV_Mic_sendDisable();
void DRV_Mic_Enable(void);
void DRV_Mic_Disable(void);
MIC_STATUS_ENUM DRV_Mic_State(void);
void Drv_micQueueInit();
bool Drv_micQueueEmpty(QUEUE_HEADER *pQheader);
void Drv_micClearQueue();
bool Drv_micInsertQueue(QUEUE_HEADER *pQheader,void *pEle);
void Drv_voiceDecodeDataSend();
void DRV_Mic_multiply_2(s16 *data,int datalen);
int DRV_Mic_Get_Buffer_Len();
void DRV_Mic_Encode_ADC();

#endif