#ifndef _USER_BK3231SF_H_
#define _USER_BK3231SF_H_

#include "t_define.h"

/********************************
 * reg base addr
 ********************************/
 
#define ADDR_ROM_START           0x00000000ul
#define ADDR_RAM_START           0x00400000ul
#define REG_ICU_BASE             0x00800000ul
#define REG_BK24_BASE            0x00810000ul
#define REG_FLASH_BASE           0x00820000ul
#define REG_AHB2APB_BASE         0x00F00000ul
#define REG_WDT_BASE             0x00F00000ul
#define REG_PWM_BASE             0x00F00100ul
#define REG_SPI_BASE             0x00F00200ul
#define REG_UART_BASE            0x00F00300ul
#define REG_I2C_BASE             0x00F00400ul
#define REG_GPIO_BASE            0x00F00500ul
#define REG_RTC_BASE             0x00F00600ul
#define REG_ADC_BASE             0x00F00700ul
#define REG_3DS_BASE             0x00F00800ul
#define REG_I2C1_BASE            0x00F00900ul
#define REG_TIMER_BASE           0x00F00A00ul
#define REG_XVER_BASE            0x00F10000ul
#define REG_CEVA_BASE            0x00F20000ul

/********************************
 * ICU - reg bitoffset bitmask
 ********************************/
 
#define REG_ICU_MCU_CLKSRC_CFG             	(*((volatile uint32 *) (REG_ICU_BASE + 0x00ul)))
#define REG_ICU_CORE_CLK_CFG            		(*((volatile uint32 *) (REG_ICU_BASE + 0x04ul)))
#define REG_ICU_ADC_CLK_CFG             		(*((volatile uint32 *) (REG_ICU_BASE + 0x08ul)))
#define REG_ICU_UART_CLK_CFG            		(*((volatile uint32 *) (REG_ICU_BASE + 0x0cul)))
#define REG_ICU_I2C_CLK_CFG             		(*((volatile uint32 *) (REG_ICU_BASE + 0x10ul)))
#define REG_ICU_SPI_CLK_CFG             		(*((volatile uint32 *) (REG_ICU_BASE + 0x14ul)))
#define REG_ICU_CEVA_CLK_CFG           			(*((volatile uint32 *) (REG_ICU_BASE + 0x18ul)))
#define REG_ICU_WD_CLK_CFG             			(*((volatile uint32 *) (REG_ICU_BASE + 0x1cul)))
#define REG_ICU_BK24_CLK_CFG            		(*((volatile uint32 *) (REG_ICU_BASE + 0x20ul)))
#define REG_ICU_LPO_CLK_CFG            			(*((volatile uint32 *) (REG_ICU_BASE + 0x24ul)))
#define REG_ICU_RTC_CLK_CFG             		(*((volatile uint32 *) (REG_ICU_BASE + 0x28ul)))
#define REG_ICU_PWM0_CLK_CFG            		(*((volatile uint32 *) (REG_ICU_BASE + 0x2Cul)))
#define REG_ICU_PWM1_CLK_CFG             		(*((volatile uint32 *) (REG_ICU_BASE + 0x30ul)))
#define REG_ICU_PWM2_CLK_CFG             		(*((volatile uint32 *) (REG_ICU_BASE + 0x34ul)))
#define REG_ICU_PWM3_CLK_CFG             		(*((volatile uint32 *) (REG_ICU_BASE + 0x38ul)))
#define REG_ICU_PWM4_CLK_CFG             		(*((volatile uint32 *) (REG_ICU_BASE + 0x3Cul)))
#define REG_ICU_PPH_INT_EN					        (*((volatile uint32 *) (REG_ICU_BASE + 0x40ul)))
#define REG_ICU_FIQ_IRQ_EN            			(*((volatile uint32 *) (REG_ICU_BASE + 0x44ul)))
#define REG_ICU_PPH_INT_STA       					(*((volatile uint32 *) (REG_ICU_BASE + 0x48ul)))
//#define REG_ICU_PERI_2ND_EN           			(*((volatile uint32 *) (REG_ICU_BASE + 0x4cul)))
//#define REG_ICU_ANALOG_MODE           			(*((volatile uint32 *) (REG_ICU_BASE + 0x50ul)))
//#define REG_ICU_ANALOG0_PWD           			(*((volatile uint32 *) (REG_ICU_BASE + 0x54ul)))
//#define REG_ICU_ANALOG1_PWD           			(*((volatile uint32 *) (REG_ICU_BASE + 0x58ul)))
//#define REG_ICU_DIGITAL_PWD           			(*((volatile uint32 *) (REG_ICU_BASE + 0x5cul)))
#define REG_ICU_GPIO0T3_DEEP_WAKEUP_EN      (*((volatile uint32 *) (REG_ICU_BASE + 0x60ul)))
#define REG_ICU_GPIO4_DEEP_WAKEUP_EN      	(*((volatile uint32 *) (REG_ICU_BASE + 0x64ul)))
//#define REG_ICU_RC32K_CONFG           			(*((volatile uint32 *) (REG_ICU_BASE + 0x68ul)))
//#define REG_ICU_SLEEP_TIME            			(*((volatile uint32 *) (REG_ICU_BASE + 0x6Cul)))
//#define REG_ICU_BOOST_READY_DLY           	(*((volatile uint32 *) (REG_ICU_BASE + 0x70ul)))
//#define REG_ICU_RSTNREG_LATCH             	(*((volatile uint32 *) (REG_ICU_BASE + 0x74ul)))
//#define REG_ICU_EXT_TIMER_CTRL            	(*((volatile uint32 *) (REG_ICU_BASE + 0x78ul)))
#define REG_ICU_PPH_INT_FIQ_PRIORITY_EN     (*((volatile uint32 *) (REG_ICU_BASE + 0x7Cul)))
//#define REG_ICU_DCO16M_PWD                	(*((volatile uint32 *) (REG_ICU_BASE + 0x80ul)))
//#define REG_ICU_OTP_PWD                   	(*((volatile uint32 *) (REG_ICU_BASE + 0x84ul)))
//#define REG_ICU_OTP_CSTM_CFG0             	(*((volatile uint32 *) (REG_ICU_BASE + 0x88ul)))
//#define REG_ICU_OTP_CSTM_CFG1             	(*((volatile uint32 *) (REG_ICU_BASE + 0x8Cul)))
//#define REG_ICU_OTP_CSTM_CFG2             	(*((volatile uint32 *) (REG_ICU_BASE + 0x90ul)))
//#define REG_ICU_OTP_CSTM_CFG3             	(*((volatile uint32 *) (REG_ICU_BASE + 0x94ul)))
//#define REG_ICU_JTAG_MODE                 	(*((volatile uint32 *) (REG_ICU_BASE + 0x98ul)))

#define BO_ICU_MCU_CLKSRC_SEL							0
#define BM_ICU_MCU_CLKSRC_SEL							(0x03ul<<BO_ICU_MCU_CLKSRC_SEL)

#define BO_ICU_CORE_CLK_DISEN							0
#define BM_ICU_CORE_CLK_DISEN							(0x01ul<<BO_ICU_CORE_CLK_DISEN)
#define BO_ICU_CORE_CLK_DIV							  1
#define BM_ICU_CORE_CLK_DIV							  (0x03ul<<BO_ICU_CORE_CLK_DIV)

#define BO_ICU_ADC_CLK_DISEN							0
#define BM_ICU_ADC_CLK_DISEN							(0x01ul<<BO_ICU_ADC_CLK_DISEN)
#define BO_ICU_ADC_CLK_DIV							  1
#define BM_ICU_ADC_CLK_DIV							  (0x7Ful<<BO_ICU_ADC_CLK_DIV)

#define BO_ICU_UART_CLK_DISEN							0
#define BM_ICU_UART_CLK_DISEN							(0x01ul<<BO_ICU_UART_CLK_DISEN)

#define BO_ICU_I2C0_CLK_DISEN							0
#define BM_ICU_I2C0_CLK_DISEN							(0x01ul<<BO_ICU_I2C0_CLK_DISEN)
#define BO_ICU_I2C1_CLK_DISEN							16
#define BM_ICU_I2C1_CLK_DISEN							(0x01ul<<BO_ICU_I2C1_CLK_DISEN)

#define BO_ICU_SPI_CLK_DISEN							0
#define BM_ICU_SPI_CLK_DISEN							(0x01ul<<BO_ICU_SPI_CLK_DISEN)

#define BO_ICU_CEVA_CLK_DISEN							0
#define BM_ICU_CEVA_CLK_DISEN							(0x01ul<<BO_ICU_CEVA_CLK_DISEN)

#define BO_ICU_WD_CLK_DISEN							  0
#define BM_ICU_WD_CLK_DISEN							  (0x01ul<<BO_ICU_WD_CLK_DISEN)

#define BO_ICU_BK24_CLK_DISEN							0
#define BM_ICU_BK24_CLK_DISEN							(0x01ul<<BO_ICU_BK24_CLK_DISEN)

#define BO_ICU_LPO_CLK_DISEN							0
#define BM_ICU_LPO_CLK_DISEN							(0x01ul<<BO_ICU_LPO_CLK_DISEN)
#define BO_ICU_LPO_CLK_32SRC_SEL					1
#define BM_ICU_LPO_CLK_32SRC_SEL					(0x01ul<<BO_ICU_LPO_CLK_32SRC_SEL)

#define BO_ICU_RTC_CLK_DISEN							0
#define BM_ICU_RTC_CLK_DISEN							(0x01ul<<BO_ICU_RTC_CLK_DISEN)

#define BO_ICU_PWM0_CLK_DISEN							0
#define BM_ICU_PWM0_CLK_DISEN							(0x01ul<<BO_ICU_PWM0_CLK_DISEN)
#define BO_ICU_PWM0_CLK_SEL							  1
#define BM_ICU_PWM0_CLK_SEL							  (0x03ul<<BO_ICU_PWM0_CLK_SEL)

#define BO_ICU_PWM1_CLK_DISEN							0
#define BM_ICU_PWM1_CLK_DISEN							(0x01ul<<BO_ICU_PWM1_CLK_DISEN)
#define BO_ICU_PWM1_CLK_SEL							  1
#define BM_ICU_PWM1_CLK_SEL							  (0x03ul<<BO_ICU_PWM1_CLK_SEL)

#define BO_ICU_PWM2_CLK_DISEN							0
#define BM_ICU_PWM2_CLK_DISEN							(0x01ul<<BO_ICU_PWM2_CLK_DISEN)
#define BO_ICU_PWM2_CLK_SEL							  1
#define BM_ICU_PWM2_CLK_SEL							  (0x03ul<<BO_ICU_PWM2_CLK_SEL)

#define BO_ICU_PWM3_CLK_DISEN							0
#define BM_ICU_PWM3_CLK_DISEN							(0x01ul<<BO_ICU_PWM3_CLK_DISEN)
#define BO_ICU_PWM3_CLK_SEL							  1
#define BM_ICU_PWM3_CLK_SEL							  (0x03ul<<BO_ICU_PWM3_CLK_SEL)

#define BO_ICU_PWM4_CLK_DISEN							0
#define BM_ICU_PWM4_CLK_DISEN							(0x01ul<<BO_ICU_PWM4_CLK_DISEN)
#define BO_ICU_PWM4_CLK_SEL							  1
#define BM_ICU_PWM4_CLK_SEL							  (0x03ul<<BO_ICU_PWM4_CLK_SEL)
#define BO_ICU_PWM5_CLK_DISEN							4
#define BM_ICU_PWM5_CLK_DISEN							(0x01ul<<BO_ICU_PWM5_CLK_DISEN)
#define BO_ICU_PWM5_CLK_SEL							  5
#define BM_ICU_PWM5_CLK_SEL							  (0x03ul<<BO_ICU_PWM5_CLK_SEL)
#define BO_ICU_TIMER_CLK_DISEN					  8
#define BM_ICU_TIMER_CLK_DISEN						(0x01ul<<BO_ICU_TIMER_CLK_DISEN)
#define BO_ICU_TIMER_CLK_SEL							9
#define BM_ICU_TIMER_CLK_SEL							(0x01ul<<BO_ICU_TIMER_CLK_SEL)

#define BO_ICU_INT_CEVA                0
#define BO_ICU_INT_GPIO                1
#define BO_ICU_INT_BK24                2
#define BO_ICU_INT_PWM                 3
#define BO_ICU_INT_UART                4
#define BO_ICU_INT_RTC                 5
#define BO_ICU_INT_ADC                 6
#define BO_ICU_INT_SPI                 7
#define BO_ICU_INT_I2C0                8
#define BO_ICU_INT_3DS                 9
#define BO_ICU_INT_EXT_TIME            10
#define BO_ICU_INT_I2C1                11
#define BO_ICU_INT_TIMER               12
#define BO_ICU_INT_CEVA_WAKEUP                16
#define BO_ICU_INT_GPIO_WAKEUP                17
#define BO_ICU_INT_BK24_WAKEUP                18
#define BO_ICU_INT_PWM_WAKEUP                 19
#define BO_ICU_INT_UART_WAKEUP                20
#define BO_ICU_INT_RTC_WAKEUP                 21
#define BO_ICU_INT_ADC_WAKEUP                 22
#define BO_ICU_INT_SPI_WAKEUP                 23
#define BO_ICU_INT_I2C0_WAKEUP                24
#define BO_ICU_INT_3DS_WAKEUP                 25
#define BO_ICU_INT_EXT_TIME_WAKEUP            26
#define BO_ICU_INT_I2C1_WAKEUP                27
#define BO_ICU_INT_TIMER_WAKEUP               28

#define BM_ICU_INT_CEVA                (0x01ul<<BO_ICU_INT_CEVA)
#define BM_ICU_INT_GPIO                (0x01ul<<BO_ICU_INT_GPIO)
#define BM_ICU_INT_BK24                (0x01ul<<BO_ICU_INT_BK24)
#define BM_ICU_INT_PWM                 (0x01ul<<BO_ICU_INT_PWM)
#define BM_ICU_INT_UART                (0x01ul<<BO_ICU_INT_UART)
#define BM_ICU_INT_RTC                 (0x01ul<<BO_ICU_INT_RTC)
#define BM_ICU_INT_ADC                 (0x01ul<<BO_ICU_INT_ADC)
#define BM_ICU_INT_SPI                 (0x01ul<<BO_ICU_INT_SPI)
#define BM_ICU_INT_I2C0                (0x01ul<<BO_ICU_INT_I2C0)
#define BM_ICU_INT_3DS                 (0x01ul<<BO_ICU_INT_3DS)
#define BM_ICU_INT_EXT_TIME            (0x01ul<<BO_ICU_INT_EXT_TIME)
#define BM_ICU_INT_I2C1                (0x01ul<<BO_ICU_INT_I2C1)
#define BM_ICU_INT_TIMER               (0x01ul<<BO_ICU_INT_TIMER)
#define BM_ICU_INT_CEVA_WAKEUP         (0x01ul<<BO_ICU_INT_CEVA_WAKEUP)       
#define BM_ICU_INT_GPIO_WAKEUP         (0x01ul<<BO_ICU_INT_GPIO_WAKEUP)       
#define BM_ICU_INT_BK24_WAKEUP         (0x01ul<<BO_ICU_INT_BK24_WAKEUP)       
#define BM_ICU_INT_PWM_WAKEUP          (0x01ul<<BO_ICU_INT_PWM_WAKEUP)       
#define BM_ICU_INT_UART_WAKEUP         (0x01ul<<BO_ICU_INT_UART_WAKEUP)       
#define BM_ICU_INT_RTC_WAKEUP          (0x01ul<<BO_ICU_INT_RTC_WAKEUP)       
#define BM_ICU_INT_ADC_WAKEUP          (0x01ul<<BO_ICU_INT_ADC_WAKEUP)       
#define BM_ICU_INT_SPI_WAKEUP          (0x01ul<<BO_ICU_INT_SPI_WAKEUP)       
#define BM_ICU_INT_I2C0_WAKEUP         (0x01ul<<BO_ICU_INT_I2C0_WAKEUP)       
#define BM_ICU_INT_3DS_WAKEUP          (0x01ul<<BO_ICU_INT_3DS_WAKEUP)       
#define BM_ICU_INT_EXT_TIME_WAKEUP     (0x01ul<<BO_ICU_INT_EXT_TIME_WAKEUP)       
#define BM_ICU_INT_I2C1_WAKEUP         (0x01ul<<BO_ICU_INT_I2C1_WAKEUP)       
#define BM_ICU_INT_TIMER_WAKEUP        (0x01ul<<BO_ICU_INT_TIMER_WAKEUP)   

#define BO_ICU_INT_IRQ_EN                0
#define BM_ICU_INT_IRQ_EN                (0x01<<BO_ICU_INT_IRQ_EN)
#define BO_ICU_INT_FIQ_EN                1
#define BM_ICU_INT_FIQ_EN                (0x01<<BO_ICU_INT_FIQ_EN)

#define BO_ICU_DEEP_SLEEP_CTRL_WORD				16
#define BM_ICU_DEEP_SLEEP_CTRL_WORD				(0xFFFFuL<<BO_ICU_DEEP_SLEEP_CTRL_WORD)


/********************************
 * GPIO - reg bitoffset bitmask
 ********************************/
 
#define REG_GPIO0_CFG              (*((volatile uint32 *)   (REG_GPIO_BASE + 0x00ul) ))
#define REG_GPIO0_DATA             (*((volatile uint32 *)   (REG_GPIO_BASE + 0x04ul) ))
#define REG_GPIO1_CFG              (*((volatile uint32 *)   (REG_GPIO_BASE + 0x08ul) ))
#define REG_GPIO1_DATA             (*((volatile uint32 *)   (REG_GPIO_BASE + 0x0Cul) ))
#define REG_GPIO2_CFG              (*((volatile uint32 *)   (REG_GPIO_BASE + 0x10ul) ))
#define REG_GPIO2_DATA             (*((volatile uint32 *)   (REG_GPIO_BASE + 0x14ul) ))
#define REG_GPIO3_CFG              (*((volatile uint32 *)   (REG_GPIO_BASE + 0x18ul) ))
#define REG_GPIO3_DATA             (*((volatile uint32 *)   (REG_GPIO_BASE + 0x1Cul) ))
#define REG_GPIO4_CFG              (*((volatile uint32 *)   (REG_GPIO_BASE + 0x20ul) ))
#define REG_GPIO4_DATA             (*((volatile uint32 *)   (REG_GPIO_BASE + 0x24ul) ))

#define REG_GPIO0T3_INT_EDGE       (*((volatile uint32 *)   (REG_GPIO_BASE + 0x40ul) ))
#define REG_GPIO0T3_INT_EN		     (*((volatile uint32 *)   (REG_GPIO_BASE + 0x48ul) ))
#define REG_GPIO0T3_INT_STA	       (*((volatile uint32 *)   (REG_GPIO_BASE + 0x50ul) ))
#define REG_GPIO4_INT_EDGE         (*((volatile uint32 *)   (REG_GPIO_BASE + 0x44ul) ))
#define REG_GPIO4_INT_EN		       (*((volatile uint32 *)   (REG_GPIO_BASE + 0x4Cul) ))
#define REG_GPIO4_INT_STA		       (*((volatile uint32 *)   (REG_GPIO_BASE + 0x54ul) ))

#define BO_GPIO_MODE              0
#define BO_GPIO_IO_OUT_NOR        8
#define BO_GPIO_PULL_UP           16
#define BO_GPIO_PULL_DOWN         24
#define BO_GPIO_OUT_DATA          0
#define BO_GPIO_IN_DATA           8
#define BO_GPIO_IO_IN             16

#define BM_GPIO_MODE              (0x01ul<<BO_GPIO_MODE)
#define BM_GPIO_IO_OUT_NOR        (0x01ul<<BO_GPIO_IO_OUT_NOR)
#define BM_GPIO_PULL_UP           (0x01ul<<BO_GPIO_PULL_UP)
#define BM_GPIO_PULL_DOWN         (0x01ul<<BO_GPIO_PULL_DOWN)
#define BM_GPIO_OUT_DATA          (0x01ul<<BO_GPIO_OUT_DATA)
#define BM_GPIO_IN_DATA           (0x01ul<<BO_GPIO_IN_DATA)
#define BM_GPIO_IO_IN             (0x01ul<<BO_GPIO_IO_IN)

#define BO_GPIO0_INT               0
#define BO_GPIO1_INT               8
#define BO_GPIO2_INT               16
#define BO_GPIO3_INT               24
#define BO_GPIO4_INT               0

#define BM_GPIO0_INT               (0x01ul<<BO_GPIO0_INT)
#define BM_GPIO1_INT               (0x01ul<<BO_GPIO1_INT)
#define BM_GPIO2_INT               (0x01ul<<BO_GPIO2_INT)
#define BM_GPIO3_INT               (0x01ul<<BO_GPIO3_INT)
#define BM_GPIO4_INT               (0x01ul<<BO_GPIO4_INT)


/********************************
 * UART - reg bitoffset bitmask
 ********************************/
 
#define REG_UART_CFG               (*((volatile uint32 *)   (REG_UART_BASE + 0x00ul) ))
#define REG_UART_FIFO_CFG    			 (*((volatile uint32 *)   (REG_UART_BASE + 0x04ul) ))
#define REG_UART_FIFO_STA          (*((volatile uint32 *)   (REG_UART_BASE + 0x08ul) ))
#define REG_UART_DATA              (*((volatile uint32 *)   (REG_UART_BASE + 0x0Cul) ))
#define REG_UART_INT_EN		         (*((volatile uint32 *)   (REG_UART_BASE + 0x10ul) ))
#define REG_UART_INT_STA           (*((volatile uint32 *)   (REG_UART_BASE + 0x14ul) ))
#define REG_UART_FLOW_CTRL         (*((volatile uint32 *)   (REG_UART_BASE + 0x18ul) ))
#define REG_UART_WAKEUP_CFG        (*((volatile uint32 *)   (REG_UART_BASE + 0x1cul) ))

//gen cfg
#define BO_UART_TX_EN                  0
#define BO_UART_RX_EN                  1
#define BO_UART_IRDA_MODE              2
#define BO_UART_DATA_LEN               3
#define BO_UART_PARITY_EN              5
#define BO_UART_PARITY_MODE            6
#define BO_UART_STOP_LEN               7
#define BO_UART_CLK_DIV                8

#define BM_UART_TX_EN                  (0x01ul<<BO_UART_TX_EN)
#define BM_UART_RX_EN                  (0x01ul<<BO_UART_RX_EN)
#define BM_UART_IRDA_MODE              (0x01ul<<BO_UART_IRDA_MODE)
#define BM_UART_DATA_LEN               (0x03ul<<BO_UART_DATA_LEN)
#define BM_UART_PARITY_EN              (0x01ul<<BO_UART_PARITY_EN)
#define BM_UART_PARITY_MODE            (0x01ul<<BO_UART_PARITY_MODE)
#define BM_UART_STOP_LEN               (0x01ul<<BO_UART_STOP_LEN)
#define BM_UART_CLK_DIV                (0x1FFFul<<BO_UART_CLK_DIV)

//fifo cfg
#define BO_UART_TX_FIFO_THRESHOLD           0
#define BO_UART_RX_FIFO_THRESHOLD           8
#define BO_UART_RX_STOP_DETECT_TIME         16

#define BM_UART_TX_FIFO_THRESHOLD           (0xFFul<<BO_UART_TX_FIFO_THRESHOLD)
#define BM_UART_RX_FIFO_THRESHOLD           (0xFFul<<BO_UART_RX_FIFO_THRESHOLD)
#define BM_UART_RX_STOP_DETECT_TIME         (0x03ul<<BO_UART_RX_STOP_DETECT_TIME)

//fifo sta
#define BO_UART_TX_FIFO_CNT                 0
#define BO_UART_RX_FIFO_CNT                 8
#define BO_UART_TX_FIFO_FULL                16 
#define BO_UART_TX_FIFO_EMPTY               17
#define BO_UART_RX_FIFO_FULL                18
#define BO_UART_RX_FIFO_EMPTY               19
#define BO_UART_TX_FIFO_WR_READY            20
#define BO_UART_RX_FIFO_RD_READY            21

#define BM_UART_TX_FIFO_CNT                 (0xFFul<<BO_UART_TX_FIFO_CNT)
#define BM_UART_RX_FIFO_CNT                 (0xFFul<<BO_UART_RX_FIFO_CNT)
#define BM_UART_TX_FIFO_FULL                (0x01ul<<BO_UART_TX_FIFO_FULL)
#define BM_UART_TX_FIFO_EMPTY               (0x01ul<<BO_UART_TX_FIFO_EMPTY)
#define BM_UART_RX_FIFO_FULL                (0x01ul<<BO_UART_RX_FIFO_FULL)
#define BM_UART_RX_FIFO_EMPTY               (0x01ul<<BO_UART_RX_FIFO_EMPTY)
#define BM_UART_TX_FIFO_WR_READY            (0x01ul<<BO_UART_TX_FIFO_WR_READY)
#define BM_UART_RX_FIFO_RD_READY            (0x01ul<<BO_UART_RX_FIFO_RD_READY)

//uart data
#define BO_UART_DATA_TX_RNTRY                 0
#define BO_UART_DATA_RX_ENTRY                 8
#define BM_UART_DATA_TX_RNTRY                 (0xFFul<<BO_UART_DATA_TX_RNTRY)
#define BM_UART_DATA_RX_ENTRY                 (0xFFul<<BO_UART_DATA_RX_ENTRY)


//int en
#define BO_UART_TX_FIFO_NEED_WRITE_EN           0
#define BO_UART_RX_FIFO_NEED_READ_EN		        1
#define BO_UART_RX_FIFO_OVER_FLOW_EN        		2
#define BO_UART_RX_PARITY_ERR_EN       					3
#define BO_UART_RX_STOP_ERR_EN         					4
#define BO_UART_TX_STOP_END_EN         					5
#define BO_UART_RX_STOP_END_EN         					6
#define BO_UART_RX_WAKEUP_EN		           			7

#define BM_UART_TX_FIFO_NEED_WRITE_EN       (0x01ul<<BO_UART_TX_FIFO_NEED_WRITE_EN) 
#define BM_UART_RX_FIFO_NEED_READ_EN        (0x01ul<<BO_UART_RX_FIFO_NEED_READ_EN) 
#define BM_UART_RX_FIFO_OVER_FLOW_EN        (0x01ul<<BO_UART_RX_FIFO_OVER_FLOW_EN) 
#define BM_UART_RX_PARITY_ERR_EN       			(0x01ul<<BO_UART_RX_PARITY_ERR_EN) 
#define BM_UART_RX_STOP_ERR_EN         			(0x01ul<<BO_UART_RX_STOP_ERR_EN) 
#define BM_UART_TX_STOP_END_EN         			(0x01ul<<BO_UART_TX_STOP_END_EN) 
#define BM_UART_RX_STOP_END_EN         			(0x01ul<<BO_UART_RX_STOP_END_EN) 
#define BM_UART_RX_WAKEUP_EN           			(0x01ul<<BO_UART_RX_WAKEUP_EN)

//int sta
#define BO_UART_TX_FIFO_NEED_WRITE        0
#define BO_UART_RX_FIFO_NEED_READ         1
#define BO_UART_RX_FIFO_OVER_FLOW         2
#define BO_UART_RX_PARITY_ERR       			3
#define BO_UART_RX_STOP_ERR         			4
#define BO_UART_TX_STOP_END         			5
#define BO_UART_RX_STOP_END         			6
#define BO_UART_RX_WAKEUP           			7

#define BM_UART_TX_FIFO_NEED_WRITE       (0x01ul<<BO_UART_TX_FIFO_NEED_WRITE) 
#define BM_UART_RX_FIFO_NEED_READ        (0x01ul<<BO_UART_RX_FIFO_NEED_READ) 
#define BM_UART_RX_FIFO_OVER_FLOW        (0x01ul<<BO_UART_RX_FIFO_OVER_FLOW) 
#define BM_UART_RX_PARITY_ERR       		 (0x01ul<<BO_UART_RX_PARITY_ERR) 
#define BM_UART_RX_STOP_ERR         		 (0x01ul<<BO_UART_RX_STOP_ERR) 
#define BM_UART_TX_STOP_END         		 (0x01ul<<BO_UART_TX_STOP_END) 
#define BM_UART_RX_STOP_END         		 (0x01ul<<BO_UART_RX_STOP_END) 
#define BM_UART_RX_WAKEUP           		 (0x01ul<<BO_UART_RX_WAKEUP)

//flow cfg

//wake cfg


/********************************
 * ADC - reg bitoffset bitmask
 ********************************/

#define REG_ADC_CFG                (*((volatile uint32 *)   (REG_ADC_BASE + 0x00ul)))
#define REG_ADC_DATA               (*((volatile uint32 *)   (REG_ADC_BASE + 0x04ul)))
	
#define BO_ADC_MODE                    0
#define BO_ADC_EN                      2
#define BO_ADC_CHNL                    3
#define BO_ADC_FIFO_EMPTY              6
#define BO_ADC_BUSY               		 7
#define BO_ADC_SAMP_RATE             	 8
#define BO_ADC_START_WAIT        	     10
#define BO_ADC_VALID_MODE              11
#define BO_ADC_INT_CLEAR               15
#define BO_ADC_CLK_DIV                 16
#define BM_ADC_MODE                    (0x03ul << BO_ADC_MODE)
#define BM_ADC_EN                      (0x01ul << BO_ADC_EN)
#define BM_ADC_CHNL                    (0x07ul << BO_ADC_CHNL)
#define BM_ADC_FIFO_EMPTY              (0x01ul << BO_ADC_FIFO_EMPTY)
#define BM_ADC_BUSY                    (0x01ul << BO_ADC_BUSY)
#define BM_ADC_SAMPLE_RATE             (0x03ul << BO_ADC_SAMP_RATE)
#define BM_ADC_WAIT_CLK_SET        		 (0x01ul << BO_ADC_START_WAIT)
#define BM_ADC_VALID_MODE              (0x03ul << BO_ADC_VALID_MODE)
#define BM_ADC_INT_CLEAR               (0x01ul << BO_ADC_INT_CLEAR)
#define BM_ADC_CLK_RATE                (0x07ul << BO_ADC_CLK_DIV)

#define BO_ADC_DATA                    2
#define BM_ADC_DATA                    (0xFFul << BO_ADC_DATA)

/********************************
 * PWM - reg bitoffset bitmask
 ********************************/
 
#define REG_PWM_CFG     (*( (volatile uint32 *)   (REG_PWM_BASE + (0x00ul)) ))
#define REG_PWM_INT_STA (*( (volatile uint32 *)   (REG_PWM_BASE + (0x04ul)) )) 
#define REG_PWM0_CNT    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x08ul)) ))
#define REG_PWM0_CAP    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x0Cul)) ))
#define REG_PWM1_CNT    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x10ul)) ))
#define REG_PWM1_CAP    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x14ul)) ))
#define REG_PWM2_CNT    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x18ul)) ))
#define REG_PWM2_CAP    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x1Cul)) ))
#define REG_PWM3_CNT    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x20ul)) ))
#define REG_PWM3_CAP    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x24ul)) ))
#define REG_PWM4_CNT    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x28ul)) ))
#define REG_PWM4_CAP    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x2Cul)) ))
#define REG_PWM5_CNT    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x30ul)) ))
#define REG_PWM5_CAP    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x34ul)) ))
#define REG_PWM6_CNT    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x38ul)) ))
#define REG_PWM6_CAP    (*( (volatile uint32 *)   (REG_PWM_BASE + (0x3Cul)) ))
	
#define BO_PWM_EN					0
#define BO_PWM_INT_EN			1
#define BO_PWM_MODE				2
#define BM_PWM_EN					(0x01ul<<BO_PWM_EN)
#define BM_PWM_INT_EN			(0x01ul<<BO_PWM_INT_EN)
#define BM_PWM_MODE				(0x03ul<<BO_PWM_MODE)

#define BO_PWM0_INT_STA				0	
#define BO_PWM1_INT_STA				1	
#define BO_PWM2_INT_STA				2	
#define BO_PWM3_INT_STA				3	
#define BO_PWM4_INT_STA				4	
#define BO_PWM5_INT_STA				5
#define BM_PWM0_INT_STA				(0x01ul<<BO_PWM0_INT_STA)	
#define BM_PWM1_INT_STA				(0x01ul<<BO_PWM1_INT_STA)	
#define BM_PWM2_INT_STA				(0x01ul<<BO_PWM2_INT_STA)	
#define BM_PWM3_INT_STA				(0x01ul<<BO_PWM3_INT_STA)	
#define BM_PWM4_INT_STA				(0x01ul<<BO_PWM4_INT_STA)
#define BM_PWM5_INT_STA				(0x01ul<<BO_PWM5_INT_STA)

#define BO_PWM_CNT_PERIOD					0
#define BO_PWM_CNT_DUTY					  16
#define BM_PWM_CNT_PERIOD					(0xFFFFul<<BO_PWM_CNT_PERIOD)
#define BM_PWM_CNT_DUTY					  (0xFFFFul<<BO_PWM_CNT_DUTY)

#define BO_PWM_CNT_CAP				0	
#define BM_PWM_CNT_CAP				(0xFFFFul<<BO_PWM_CNT_CAP)

/********************************
 * TIMER - reg bitoffset bitmask
 ********************************/

#define REG_TIMER_CFG     			(*( (volatile uint32 *)   (REG_TIMER_BASE + 0x00ul) ))
#define REG_TIMER_INT_STA     	(*( (volatile uint32 *)   (REG_TIMER_BASE + 0x04ul) )) 
#define REG_TIMER0_PERIOD_CNT  	(*( (volatile uint32 *)   (REG_TIMER_BASE + 0x08ul) ))
#define REG_TIMER0_CNT  				(*( (volatile uint32 *)   (REG_TIMER_BASE + 0x0Cul) ))
#define REG_TIMER1_PERIOD_CNT  	(*( (volatile uint32 *)   (REG_TIMER_BASE + 0x10ul) ))
#define REG_TIMER1_CNT	  			(*( (volatile uint32 *)   (REG_TIMER_BASE + 0x14ul) ))
	
#define BO_TIMER_EN					0
#define BO_TIMER_INT_EN			1
#define BM_TIMER_EN					(0x01ul<<BO_TIMER_EN)
#define BM_TIMER_INT_EN			(0x01ul<<BO_TIMER_INT_EN)

#define BO_TIMER0_INT_STA		0
#define BO_TIMER1_INT_STA		1
#define BM_TIMER0_INT_STA		(0x01ul<<BO_TIMER0_INT_STA)
#define BM_TIMER1_INT_STA		(0x01ul<<BO_TIMER1_INT_STA)

#define BO_TIMER_PERIOD_CNT			0
#define BM_TIMER_PERIOD_CNT			(0xFFFFul<<BO_TIMER_PERIOD_CNT)

#define BO_TIMER_CNT						0
#define BM_TIMER_CNT						(0xFFFFul<<BO_TIMER_CNT)

/********************************
 * RTC - reg bitoffset bitmask
 ********************************/

#define REG_RTC_CFG                (*((volatile uint32 *)   (REG_RTC_BASE + 0x00ul) ))
#define REG_RTC_CLK_CFG            (*((volatile uint32 *)   (REG_RTC_BASE + 0x04ul) ))
#define REG_RTC_TIME               (*((volatile uint32 *)   (REG_RTC_BASE + 0x08ul) ))
#define REG_RTC_ALM_TIME           (*((volatile uint32 *)   (REG_RTC_BASE + 0x0Cul) ))
#define REG_RTC_ALM_FLAG           (*((volatile uint32 *)   (REG_RTC_BASE + 0x10ul) ))
	
#define BO_RTC_EN                  0
#define BO_RTC_REST 							 1
#define BO_RTC_ALARM_EN            2
#define BO_RTC_ALARM_MODE          3
#define BM_RTC_EN                  
#define BM_RTC_REST               
#define BM_RTC_ALARM_EN            
#define BM_RTC_ALARM_MODE          

#define BO_RTC_DIV                      0
#define BO_RTC_UNIT_MSEC                2
#define BO_RTC_UNIT_SEC                 8
#define BM_RTC_DIV                     
#define BM_RTC_UNIT_MSEC                 
#define BM_RTC_UNIT_SEC                  

#define BO_RTC_SECOND                  0
#define BO_RTC_MINUTE                  6
#define BO_RTC_HOUR                    12
#define BO_RTC_WEEK                    17
#define BM_RTC_SECOND                  0
#define BM_RTC_MINUTE                  6
#define BM_RTC_HOUR                    12
#define BM_RTC_WEEK                    17

#define BO_RTC_ALARM_SECOND            0
#define BO_RTC_ALARM_MINUTE            6
#define BO_RTC_ALARM_HOUR              12
#define BO_RTC_ALARM_MILLISEC          17
#define BM_RTC_ALARM_SECOND            0
#define BM_RTC_ALARM_MINUTE            6
#define BM_RTC_ALARM_HOUR              12
#define BM_RTC_ALARM_MILLISEC          17



/********************************
 * 3DS - reg bitoffset bitmask
 ********************************/
 


#endif