yc11xx_qspi.c 9.8 KB

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  1. #include "yc11xx_qspi.h"
  2. #define QSPI_BUSYTIMEOUT (0x1000000)
  3. #define DMA_WAIT_TIMEOUT (0x10000)
  4. void __attribute__((noinline)) SetLockQSPI( )
  5. {
  6. HWRITE(mem_lock_qspi, 1);
  7. }
  8. void __attribute__((noinline)) SetReleaseQSPI( )
  9. {
  10. HWRITE(mem_lock_qspi, 0);
  11. }
  12. void __attribute__((noinline)) prefetch(void *start_addr, void *end_addr)
  13. {
  14. int addr= 0;
  15. for(addr = (int)start_addr & (~0x1f);addr < (int)end_addr + 96;addr += 32)
  16. {
  17. *(volatile int*)addr = 0;
  18. }
  19. }
  20. void qspi_dma_start(void *src,int srclen,void *dst,int dstlen)
  21. {
  22. HWRITEW(CORE_QSPI_TXADDR,(int)src);
  23. HWRITEW(CORE_QSPI_TXLEN,srclen);
  24. HWRITEW(CORE_QSPI_RXADDR,(int)dst);
  25. HWRITEW(CORE_QSPI_RXLEN,dstlen);
  26. HWRITE(CORE_DMA_START,8);
  27. }
  28. uint8_t qspi_dma_wait(void)
  29. {
  30. int timeout = 0;
  31. while(!(HREAD(CORE_DMA_STATUS) & 8))
  32. {
  33. timeout++;
  34. if(timeout>DMA_WAIT_TIMEOUT)
  35. {
  36. return ERROR;
  37. }
  38. }
  39. return SUCCESS;
  40. }
  41. /*
  42. * @brief: qspi_write (spi mode)
  43. * @param: tbuf data buffer
  44. * @param: len data len
  45. * @return: ERROR ,SUCCESS
  46. */
  47. uint8_t qspi_write(uint8_t *tbuf,uint32_t len)
  48. {
  49. uint8_t ctrl = HREAD(CORE_QSPI_CTRL);
  50. uint8_t delay = HREAD(CORE_QSPI_DELAY);
  51. uint8_t ret = 0;
  52. HWRITE(CORE_QSPI_CTRL, 0x44);
  53. HWRITE(CORE_QSPI_DELAY,0x80);
  54. qspi_dma_start(tbuf, len, 0, 0);
  55. ret = qspi_dma_wait();
  56. HWRITE(CORE_QSPI_CTRL, ctrl);
  57. HWRITE(CORE_QSPI_DELAY, delay);
  58. return ret;
  59. }
  60. /*
  61. * @brief:qspi_read_write (spi mode)
  62. * @param:tbuf
  63. * @param:tlen
  64. * @param:rbuf
  65. * @param:rlen
  66. * @return: none
  67. */
  68. uint8_t qspi_read_write(uint8_t *tbuf,uint32_t tlen,uint8_t *rbuf,uint32_t rlen)
  69. {
  70. uint8_t ctrl = HREAD(CORE_QSPI_CTRL);
  71. uint8_t delay = HREAD(CORE_QSPI_DELAY);
  72. uint8_t ret = 0;
  73. HWRITE(CORE_QSPI_CTRL, 0x44);
  74. HWRITE(CORE_QSPI_DELAY,0x80);
  75. qspi_dma_start(tbuf, tlen, rbuf, rlen);
  76. ret = qspi_dma_wait();
  77. HWRITE(CORE_QSPI_CTRL, ctrl);
  78. HWRITE(CORE_QSPI_DELAY,delay);
  79. return ret;
  80. }
  81. /*
  82. * @brief: write flash cmd
  83. * @param: cmd
  84. * @return: ERROR ,SUCCESS
  85. */
  86. uint8_t qspi_flash_cmd(uint8_t cmd)
  87. {
  88. uint8_t tbuf[1];
  89. tbuf[0] = cmd;
  90. return qspi_write(tbuf, 1);
  91. }
  92. /*
  93. * @brief:read flash status1
  94. * @param:cmd
  95. * @return: ERROR ,SUCCESS
  96. */
  97. uint8_t qspi_flash_readstatus1(uint8_t *rbuf)
  98. {
  99. uint8_t tbuf[1];
  100. tbuf[0] = FlashCMD_ReadRegister1;
  101. return qspi_read_write(tbuf, 1, rbuf, 1);
  102. }
  103. /*
  104. * @brief:read flash status2
  105. * @param:cmd
  106. * @return: ERROR ,SUCCESS
  107. */
  108. uint8_t qspi_flash_readstatus2(uint8_t *rbuf)
  109. {
  110. uint8_t tbuf[1];
  111. tbuf[0] = FlashCMD_ReadRegister2;
  112. return qspi_read_write(tbuf, 1, rbuf, 1);
  113. }
  114. uint8_t qspi_flash_waitfinish(void)
  115. {
  116. uint32_t timeout = 0;
  117. uint8_t status1=1;
  118. while(status1 & 1)
  119. {
  120. qspi_flash_readstatus1(&status1);
  121. if(++timeout > QSPI_BUSYTIMEOUT)
  122. {
  123. return ERROR;
  124. }
  125. }
  126. return SUCCESS;
  127. }
  128. /*
  129. * @brief:write flash reg reg[0] s7~0 reg[1] s15~0
  130. * @param:rxbuf
  131. * @return: ERROR ,SUCCESS
  132. */
  133. uint8_t qspi_flash_writestatus(uint8_t *reg)
  134. {
  135. uint8_t tbuf[3];
  136. tbuf[0] = FlashCMD_WriteRegister;
  137. tbuf[1] = reg[0];
  138. tbuf[2] = reg[1];
  139. if(ERROR == qspi_flash_cmd(FlashCMD_WriteEnable))
  140. return ERROR;
  141. qspi_write(tbuf, 3);
  142. return qspi_flash_waitfinish();
  143. }
  144. /*
  145. * @brief:flash write enable
  146. * @param:none
  147. * @return: ERROR ,SUCCESS
  148. */
  149. uint8_t qspi_flash_writeenable(void)
  150. {
  151. return qspi_flash_cmd(FlashCMD_WriteEnable);
  152. }
  153. /*
  154. * @brief:flash write disable
  155. * @param:none
  156. * @return: ERROR ,SUCCESS
  157. */
  158. uint8_t qspi_flash_writedisable(void)
  159. {
  160. return qspi_flash_cmd(FlashCMD_WriteDisable);
  161. }
  162. void qspi_flash_precmd(uint8_t *buf,uint8_t cmd,uint32_t addr)
  163. {
  164. buf[0] = cmd;
  165. buf[1] = addr >> 16;
  166. buf[2] = addr >> 8;
  167. buf[3] = addr;
  168. }
  169. /*
  170. * @brief: flash write
  171. * @param: flash_addr
  172. * @param: len
  173. * @param: txbuf
  174. * @return: ERROR ,SUCCESS
  175. */
  176. #define BLOCK_UNIT (256)
  177. uint8_t _qspi_flash_write(uint32_t flash_addr,uint32_t len,uint8_t *tbuf)
  178. {
  179. uint8_t buf[BLOCK_UNIT+4] = {0};
  180. uint32_t packnum = 0;
  181. uint32_t packlen = 0;
  182. packlen = (BLOCK_UNIT - flash_addr % BLOCK_UNIT);
  183. packlen = packlen>len?len:packlen;
  184. qspi_flash_precmd(buf,FlashCMD_PageProgram,flash_addr);
  185. for(uint32_t j = 0;j<packlen;j++)
  186. {
  187. buf[4+j] = tbuf[j];
  188. }
  189. if(ERROR == qspi_flash_writeenable())
  190. return ERROR;
  191. if(ERROR == qspi_write(buf,packlen+4))
  192. return ERROR;
  193. if(ERROR == qspi_flash_waitfinish())
  194. return ERROR;
  195. flash_addr+=packlen;
  196. tbuf +=packlen;
  197. len -=packlen;
  198. packnum = (len+BLOCK_UNIT-1)/BLOCK_UNIT;
  199. for(uint32_t i=0; i<packnum;i++)
  200. {
  201. packlen = len > BLOCK_UNIT?BLOCK_UNIT:len;
  202. qspi_flash_precmd(buf,FlashCMD_PageProgram,flash_addr+i*BLOCK_UNIT);
  203. for(uint32_t j = 0;j<packlen;j++)
  204. {
  205. buf[4+j] = tbuf[j+i*BLOCK_UNIT];
  206. }
  207. if(ERROR == qspi_flash_writeenable())
  208. return ERROR;
  209. if(ERROR == qspi_write(buf,packlen+4))
  210. return ERROR;
  211. if(ERROR == qspi_flash_waitfinish())
  212. return ERROR;
  213. len -= packlen;
  214. }
  215. return SUCCESS;
  216. }
  217. /*
  218. * @brief:chip erase
  219. * @param:none
  220. * @return: ERROR ,SUCCESS
  221. */
  222. uint8_t _qspi_flash_chiperase(void)
  223. {
  224. if(ERROR == qspi_flash_writeenable())
  225. return ERROR;
  226. if(ERROR == qspi_flash_cmd(FlashCMD_ChipErase))
  227. return ERROR;
  228. return qspi_flash_waitfinish();
  229. }
  230. /*
  231. * @brief:qspi_flash_erase
  232. * @param:cmd
  233. * W25X_SECTOR_ERASE 4K
  234. * W25X_BLOCK_ERASE32K 32k
  235. * W25X_BLOCK_ERASE64K 64k
  236. * @param:flash_addr
  237. * @return: none
  238. */
  239. uint8_t _qspi_flash_erase(uint8_t cmd,uint32_t flash_addr)
  240. {
  241. uint8_t tbuf[4] = {0};
  242. if(ERROR == qspi_flash_writeenable())
  243. return ERROR;
  244. qspi_flash_precmd(tbuf,cmd,flash_addr);
  245. if(ERROR == qspi_write(tbuf,4))
  246. return ERROR;
  247. return qspi_flash_waitfinish();
  248. }
  249. /*
  250. * @brief: flash read
  251. * @param: flash_addr
  252. * @param: len
  253. * @param: rxbuf
  254. * @return: ERROR ,SUCCESS
  255. */
  256. uint8_t _qspi_flash_read(uint32_t flash_addr,uint32_t rlen,uint8_t *rbuf)
  257. {
  258. uint8_t ret = 0;
  259. uint8_t tbuf[4] = {0};
  260. uint32_t tlen = 4;
  261. uint8_t ctrl = HREAD(CORE_QSPI_CTRL);
  262. uint8_t delay = HREAD(CORE_QSPI_DELAY);
  263. tbuf[0] = FlashCMD_ReadDual;
  264. tbuf[1] = flash_addr >> 16;
  265. tbuf[2] = flash_addr >> 8;
  266. tbuf[3] = flash_addr;
  267. HWRITE(CORE_QSPI_CTRL,0x45);
  268. HWRITE(CORE_QSPI_DELAY,0x8);
  269. qspi_dma_start(tbuf, tlen, rbuf, rlen);
  270. ret = qspi_dma_wait();
  271. HWRITE(CORE_QSPI_CTRL, ctrl);
  272. HWRITE(CORE_QSPI_DELAY, delay);
  273. return ret;
  274. }
  275. /*
  276. * @brief:read flash id
  277. * @param:cmd
  278. * @return: ERROR ,SUCCESS
  279. */
  280. uint32_t _qspi_flash_ManufactureID(void)
  281. {
  282. uint8_t tbuf[4]={0,0,0,0};
  283. uint8_t rbuf[2];
  284. uint32_t ret;
  285. tbuf[0] = FlashCMD_REMS;
  286. qspi_read_write(tbuf, 4, rbuf, 2);
  287. ret = ((rbuf[0]<<8) | rbuf[1]);
  288. return ret;
  289. }
  290. /*
  291. * @brief:page erase 256byte
  292. * @param:flash addr
  293. * @return: ERROR ,SUCCESS
  294. */
  295. uint8_t qspi_flash_pageerase(uint32_t flash_addr)
  296. {
  297. prefetch(qspi_dma_start, qspi_flash_sectorerase);
  298. return _qspi_flash_erase(FlashCMD_PageErase,flash_addr);
  299. }
  300. /*
  301. * @brief:sector erase 4kB
  302. * @param:flash addr
  303. * @return: ERROR ,SUCCESS
  304. */
  305. uint8_t qspi_flash_sectorerase(uint32_t flash_addr)
  306. {
  307. prefetch(qspi_dma_start, qspi_flash_sectorerase);
  308. return _qspi_flash_erase(FlashCMD_SectorErase,flash_addr);
  309. }
  310. /*
  311. * @brief:block erase 32K
  312. * @param:flash addr
  313. * @return: ERROR ,SUCCESS
  314. */
  315. uint8_t qspi_flash_blockerase32k(uint32_t flash_addr)
  316. {
  317. prefetch(qspi_dma_start, qspi_flash_blockerase32k);
  318. return _qspi_flash_erase(FlashCMD_32kErase,flash_addr);
  319. }
  320. /*
  321. * @brief:block erase 64K
  322. * @param:flash addr
  323. * @return: ERROR ,SUCCESS
  324. */
  325. uint8_t qspi_flash_blockerase64k(uint32_t flash_addr)
  326. {
  327. prefetch(qspi_dma_start, qspi_flash_blockerase64k);
  328. return _qspi_flash_erase(FlashCMD_64kErase,flash_addr);
  329. }
  330. uint8_t qspi_flash_chiperase(void)
  331. {
  332. prefetch(qspi_dma_start, qspi_flash_chiperase);
  333. return _qspi_flash_chiperase();
  334. }
  335. uint8_t qspi_flash_write(uint32_t flash_addr,uint32_t len,uint8_t *tbuf)
  336. {
  337. prefetch(qspi_dma_start, qspi_flash_write);
  338. return _qspi_flash_write(flash_addr,len,tbuf);
  339. }
  340. /*
  341. * @brief: flash read
  342. * @param: flash_addr
  343. * @param: len
  344. * @param: rxbuf
  345. * @return: ERROR ,SUCCESS
  346. */
  347. uint8_t qspi_flash_read(uint32_t flash_addr,uint32_t rlen,uint8_t *rbuf)
  348. {
  349. prefetch(qspi_dma_start, qspi_flash_read);
  350. return _qspi_flash_read(flash_addr,rlen,rbuf);
  351. }
  352. /*
  353. * @brief:read flash id
  354. * @param:cmd
  355. * @return: ERROR ,SUCCESS
  356. */
  357. uint32_t qspi_flash_ManufactureID(void)
  358. {
  359. prefetch(qspi_dma_start, qspi_flash_ManufactureID);
  360. return _qspi_flash_ManufactureID();
  361. }
  362. uint8_t QSPI_ReadFlashData(uint32_t flash_addr,uint32_t rlen,uint8_t *rbuf)
  363. {
  364. uint8_t ret;
  365. OS_ENTER_CRITICAL();
  366. SetLockQSPI( );
  367. ret = qspi_flash_read(flash_addr, rlen, rbuf);
  368. SetReleaseQSPI( );
  369. OS_EXIT_CRITICAL();
  370. return ret;
  371. }
  372. uint8_t QSPI_WriteFlashData(uint32_t flash_addr,uint32_t len,uint8_t *tbuf)
  373. {
  374. uint8_t ret;
  375. OS_ENTER_CRITICAL();
  376. SetLockQSPI( );
  377. ret = qspi_flash_write(flash_addr, len, tbuf);
  378. SetReleaseQSPI( );
  379. OS_EXIT_CRITICAL();
  380. return ret;
  381. }
  382. uint8_t QSPI_SectorEraseFlash(uint32_t flash_addr)
  383. {
  384. uint8_t ret;
  385. OS_ENTER_CRITICAL();
  386. SetLockQSPI( );
  387. ret = qspi_flash_sectorerase(flash_addr);
  388. SetReleaseQSPI( );
  389. OS_EXIT_CRITICAL();
  390. return ret;
  391. }
  392. uint8_t QSPI_PageEraseFlash(uint32_t flash_addr)
  393. {
  394. uint8_t ret;
  395. OS_ENTER_CRITICAL();
  396. SetLockQSPI( );
  397. ret = qspi_flash_pageerase(flash_addr);
  398. SetReleaseQSPI( );
  399. OS_EXIT_CRITICAL();
  400. return ret;
  401. }
  402. uint8_t QSPI_BlockEraseFlash32k(uint32_t flash_addr)
  403. {
  404. uint8_t ret;
  405. OS_ENTER_CRITICAL();
  406. SetLockQSPI( );
  407. ret = qspi_flash_blockerase32k(flash_addr);
  408. SetReleaseQSPI( );
  409. OS_EXIT_CRITICAL();
  410. return ret;
  411. }
  412. uint8_t QSPI_BlockEraseFlash64k(uint32_t flash_addr)
  413. {
  414. uint8_t ret;
  415. OS_ENTER_CRITICAL();
  416. SetLockQSPI( );
  417. ret = qspi_flash_blockerase64k(flash_addr);
  418. SetReleaseQSPI( );
  419. OS_EXIT_CRITICAL();
  420. return ret;
  421. }