/**************************************************************************************************
  Filename:       interrupt_stubs.s51
  Revised:        $Date: 2012-03-27 14:53:26 -0700 (Tue, 27 Mar 2012) $
  Revision:       $Revision: 29910 $

  Description:    Boot Loader code ISR intercept and re-direct table for 8051 SOC.


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**************************************************************************************************/

OFFSET   EQU    0x2000

                COMMON  INTVEC(1)
                ;
                ; the interrupt vectors in the boot code simply jump to the user's LJMP
                ; instruction based at the known offset defined by 'OFFSET'.

   ORG     0x0003      ; RF Tx FIFO underflow and overflow
   LJMP  $ + OFFSET
   ORG     0x000B      ; ADC end of conversion
   LJMP  $ + OFFSET
   ORG     0x0013      ; USART0 Rx complete
   LJMP  $ + OFFSET
   ORG     0x001B      ; USART1 Rx complete
   LJMP  $ + OFFSET
   ORG     0x0023      ; AES encryption/decryption complete
   LJMP  $ + OFFSET
   ORG     0x002B      ; Sleep timer compare
   LJMP  $ + OFFSET
   ORG     0x0033      ; Port 2 inputs - used by USB library.
   LJMP  $ + OFFSET
   ORG     0x003B      ; USART0 Tx complete
   LJMP  $ + OFFSET
   ORG     0x0043      ; DMA transfer complete
   LJMP  $ + OFFSET
   ORG     0x004B      ; Timer 1 (16-bit) capture/compare/overflow
   LJMP  $ + OFFSET
   ORG     0x0053      ; Timer 2 (MAC timer)
   LJMP  $ + OFFSET
   ORG     0x005B      ; Timer 3 (8-bit) capture/compare/overflow
   LJMP  $ + OFFSET
   ORG     0x0063      ; Timer 4 (8-bit) capture/compare/overflow
   LJMP  $ + OFFSET
   ORG     0x006B      ; Port 0 inputs
   LJMP  $ + OFFSET
   ORG     0x0073      ; USART1 Tx complete
   LJMP  $ + OFFSET
   ORG     0x007B      ; Port 1 inputs
   LJMP  $ + OFFSET
   ORG     0x0083      ; RF general interrupts
   LJMP  $ + OFFSET
   ORG     0x008B      ; Watchdog overflow in timer mode
   LJMP  $ + OFFSET

   END